As a Reference Board
5-2
5.1
As a Reference Board
As a reference design, the ADS8383EVM contains the essential circuitry to
showcase the analog-to-digital converter. This essential circuitry includes the
input amplifier, reference circuit, and buffers. The EVM analog input circuit is
optimized for 100 kHz sine wave, therefore users may need to adjust the
resistor and capacitor values of the A/D input RC circuit. In AC type
applications where signal distortion is a concern, polypropylene capacitors
should be used in the signal path.
5.2
As a Prototype Board
As a prototype board, the buffer circuit consists of footprint is a standard 8-pin
SOIC and resistor pads for inverting and noninverting configurations. The
ADS8383EVM can be used to evaluate both dual and single supply amplifiers.
The EVM comes installed with a dual supply amplifier as it allows the user to
take advantage of the full input voltage range of the converter. For applications
that require signal supply operation and smaller input voltage range, the
THS4031 can be replaced with the single supply amplifier like OPA300. Pad
jumper SJP6 should be shorted between pads 1 and 2, as it shorts the minus
supply pin of the amplifier to ground. Positive supply voltage can be applied
via test point TP14 or connector J1 pin 1.
5.3
As a Software Test Platform
As a software test platform, connectors P1, P2, P3 plug into the parallel
interface connectors of the 5−6K interface card. The 5−6K interface card sits
on the C5000 and C6000 Digital Signal Processor starter kit (DSK). The
ADS8383EVM is then mapped into the processor’s memory space. This card
also provides an area for signal conditioning. This area can be used to install
application circuit(s) for digitization by the ADS8383 analog-to-digital
converter. Refer to the 5−6K interface card user’s guide (SLAU104) for more
information.
For the software engineer the ADS8383EVM provides a simple platform for
interfacing to the converter. The EVM provides standard 0.1” headers and
sockets to wire into prototype boards. The user need only provide in 3 address
lines (A2, A1, A0) and address valid line(DC_CS) to connector P2. To choose
which address combinations will generate RD and CONVST set jumpers as
shown in Table 3−2. Recall chip select (CS) signal is not memory mapped or
tied to P2, therefore it must be controlled via general purpose pin or shorted
to ground at J3 pin 1. If address decoding is not required, the EVM provides
direct access to converter data bus via P3 and control via J3.