Texas Instruments ADS1282, Manual

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CLK
DVDD
DRDY
Internal Reset
1V nom
AVDD AVSS
-
3.5V nom
2
16
t
DR
f
CLK
System Clock
(f )
CLK
DRDY
RESET Pin
RESET Command
t
RST
Settled
Data
or
t
CRHD
t
DR
t
RCSU
PWDN Pin
DRDY
t
DR
Wakeup
Command
ADS1282
SBAS418I – SEPTEMBER 2007 – REVISED MARCH 2015 www.ti.com
9.20 Reset (RESET Pin and Reset Power-Down
Command) (PWDN Pin and Standby
Command) (continued)
The ADS1282 may be reset in two ways: toggle the
RESET pin low or send a Reset command. When
In power-down, note that the device outputs remain
using the RESET pin, take it low and hold for at least
active and the device inputs must not float. When the
2/f
CLK
to force a reset. The ADS1282 is held in reset
Standby command is sent, the SPI port and the
until the pin is released. By command, RESET takes
configuration registers are kept active. Figure 50 and
effect on the next rising edge of f
CLK
after the eighth
Table 12 show the timing.
rising edge of SCLK of the command. Note that in
order to ensure the Reset command can function, the
SPI interface may require resetting itself; see the
Serial Interface section.
In reset, registers are set to default and the
conversions are synchronized on the next rising edge
of CLK. New conversion data are available, as shown
in
Figure 49 and Table 11 .
Figure 50. PWDN Pin and Wake-Up Command
Timing
( Table 12 Shows t
DR
)
9.22 Power-On Sequence
The ADS1282 has three power supplies: AVDD,
AVSS, and DVDD.
Figure 51 shows the power-on
sequence of the ADS1282. The power supplies can
be sequenced in any order. The supplies [the
Figure 49. Reset Timing difference of (AVDD – AVSS) and DVDD] generate
an internal reset whose outputs are summed to
generate a global internal reset. After the supplies
Table 11. Reset Timing for Figure 49
have crossed the minimum thresholds, 2
16
f
CLK
cycles
are counted before releasing the internal reset. After
PARAMETER DESCRIPTION MIN UNITS
the internal reset is released, new conversion data
t
CRHD
CLK to RESET hold time 10 ns
are available, as shown in Figure 51 and Table 12 .
t
RCSU
RESET to CLK setup time 10 ns
t
RST
RESET low 2 1/f
CLK
62.98046875/
t
DR
Time for data ready
f
DATA
+ 468/f
CLK
9.21 Power-Down
(PWDN Pin and Standby Command)
There are two ways to power-down the ADS1282:
take the PWDN pin low or send a Standby command.
When the PWDN pin is pulled low, the internal
circuitry is disabled to minimize power and the
contents of the register settings are reset.
Figure 51. Power-On Sequence
Table 12. Power-On, PWDN Pin, and Wake-Up Command Timing for New Data
PARAMETER DESCRIPTION FILTER MODE
See Appendix , Table 35 SINC
(1)
Time for data ready 2
16
CLK cycles after power-on;
t
DR
and new data ready after PWDN pin or Wake-Up command
62.98046875/f
DATA
+ 468/f
CLK
(2)
FIR
(1) Supply power-on and PWDN pin default is 1000SPS FIR.
(2) Subtract two CLK cycles for the Wake-Up command. The Wake-Up command is timed from the next rising edge of CLK to after the
eighth rising edge of SCLK during command to DRDY falling.
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