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Texas Instruments ADS1282, Manual

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ADS1282

SCLK

DOUT1

DIN2

ADS1282

SCLK

DOUT2

FPGA or Processor

DOUT1

DIN1

DRDY1

IRQ

SCLK (optional)

SCLK

DOUT2

DIN2

DRDY2

DIN2

IRQ (optional)

DVDD

BYPAS

1.65V to 3.6V

Tie DVDD to BYPAS if

DVDD power is < 2.25V.

Otherwise float BYPAS.

ADS1282

1 F

m

ADS1282

www.ti.com

SBAS418I – SEPTEMBER 2007 – REVISED MARCH 2015

9.23 DVDD Power Supply

Serial Interface (continued)

The DVDD supply operates over the range of +1.65V

9.24.1 Serial Clock (SCLK)

to +3.6V. If DVDD is operated at less than 2.25V,

The serial clock (SCLK) is an input that is used to

connect the DVDD pin to the BYPAS pin. If DVDD is

clock data into (DIN) and out of (DOUT) the

greater than or equal to 2.25V, do not connect DVDD

ADS1282. This input is a Schmitt-trigger input that

to the BYPAS pin.

Figure 52

shows this connection.

has a high degree of noise immunity. However, it is
recommended to keep SCLK as clean as possible to
prevent possible glitches from inadvertently shifting
the data.

Data are shifted into DIN on the rising edge of SCLK
and data are shifted out of DOUT on the falling edge
of SCLK. If SCLK is held low for 64 DRDY cycles,
data transfer or commands in progress terminate and
the SPI interface resets. The next SCLK pulse starts
a new communication cycle. This timeout feature can
be used to recover the interface when a transmission

Figure 52. DVDD Power

is interrupted or SCLK inadvertently glitches. SCLK
should remain low when not active.

9.24 Serial Interface

9.24.2 Data Input (DIN)

A serial interface is used to read the conversion data

The data input pin (DIN) is used to input register data

and access the configuration registers. The interface

and commands to the ADS1282. Keep DIN low when

consists of three basic signals: SCLK, DIN, and

reading conversion data in the Read Data Continuous

DOUT. An additional output, DRDY, transitions low in

mode (except when issuing a STOP Read Data

Read Data Continuous mode when data are ready for

Continuous command). Data on DIN are shifted into

retrieval.

Figure 53

shows the connection when

the converter on the rising edge of SCLK.

multiple converters are used.

9.24.3 Data Output (DOUT)

The data output pin (DOUT) is used to output data
from the ADS1282. Data are shifted out on DOUT on
the falling edge of SCLK.

Figure 53. Interface for Multiple Devices

Copyright © 2007–2015, Texas Instruments Incorporated

Submit Documentation Feedback

25

Product Folder Links:

ADS1282

Summary of Contents for ADS1282

Page 1: ...ponse The flexible input MUX provides an additional Programmable High Pass Filter external input for measurement as well as internal Selectable FIR Data Rates 250 SPS to 4 kSPS self test connections The PGA features outstanding Filter Bypass Option low noise 5 nV Hz and high input impedance Low Power Consumption 25 mW allowing easy interfacing to geophones and hydrophones over a wide range of gain...

Page 2: ...t folder at ti com 5 Specifications 5 1 Absolute Maximum Ratings 1 Over operating free air temperature range unless otherwise noted ADS1282 ADS1282H UNIT AVDD to AVSS 0 3 to 5 5 V AVSS to DGND 2 8 to 0 3 V DVDD to DGND 0 3 to 3 9 V Input current 100 momentary mA Input current 10 continuous mA Analog input voltage AVSS 0 3 to AVDD 0 3 V Digital input voltage to DGND 0 3 to DVDD 0 3 V Maximum juncti...

Page 3: ...harmonic distortion 3 THD PGA 32 117 110 dB PGA 64 115 Spurious free dynamic dB SFDR 123 range DC PERFORMANCE Resolution No missing codes 31 Bits FIR filter mode 250 4000 SPS Data rate fDATA Sinc filter mode 8000 128 000 SPS Integral nonlinearity INL 4 Differential input 0 00005 0 0004 FSR 5 Offset error 50 200 μV Offset error after calibration 6 Shorted input 1 μV Offset drift 0 02 μV C Gain erro...

Page 4: ...lay s Linear phase filter 31 fDATA Minimum phase filter 62 fDATA Settling time latency s Linear phase filter 62 fDATA DIGITAL INPUT OUTPUT VIH 0 8 DVDD DVDD V VIL DGND 0 2 DVDD V VOH IOH 1mA 0 8 DVDD V VOL IOL 1mA 0 2 DVDD V Input leakage 0 VDIGITAL IN DVDD 10 μA Clock input fCLK 1 4 096 MHz Serial clock rate fSCLK fCLK 2 MHz POWER SUPPLY AVSS 2 6 0 V AVDD AVSS 4 75 AVSS 5 25 V DVDD 1 65 3 6 V Nor...

Page 5: ...valid to SCLK rising edge setup time 50 ns tDIHD Valid DIN to SCLK rising edge hold time 50 ns tDOPD SCLK falling edge to valid new DOUT propagation delay 2 100 ns tDOHD SCLK falling edge to DOUT invalid hold time 0 ns Final SCLK rising edge of command to first SCLK rising edge for register read write tSCDL 24 1 fCLK data Also between consecutive commands 1 Holding SCLK low for 64 DRDY falling edg...

Page 6: ...e M0 9 Digital I O M0 Modulator data output 0 Otherwise the pin is an unused input must be tied SYNC 10 Digital input Synchronize input MFLAG 11 Digital output Modulator Over Range flag 0 normal 1 modulator over range DGND 6 12 25 27 Digital ground Digital ground pin 12 is the key ground point CAPN 13 Analog PGA outputs Connect 10nF capacitor from CAPP to CAPN CAPP 14 Analog PGA outputs Connect 10...

Page 7: ... 50 Frequency Hz 0 20 40 60 80 180 Amplitude dB 100 150 500 250 350 450 200 300 400 100 120 140 160 8192 Point FFT V 0 5dBFS 31 25Hz PGA 1 THD 124 0dB IN 0 50 Frequency Hz 0 20 40 60 80 180 Amplitude dB 100 150 500 250 350 450 200 300 400 100 120 140 160 8192 Point FFT V 20dBFS 31 25Hz PGA 1 THD 120 1dB IN ADS1282 www ti com SBAS418I SEPTEMBER 2007 REVISED MARCH 2015 8 Typical Characteristics At 2...

Page 8: ...Noise Ratio dB 15 5 125 45 85 25 65 105 V 20mV IN DC 55 35 Temperature C 110 115 120 125 130 Total Harmonic Distortion dB 15 5 125 45 85 25 65 105 PGA 8 V 31 25Hz 0 5dBFS IN ADS1282 SBAS418I SEPTEMBER 2007 REVISED MARCH 2015 www ti com Typical Characteristics continued At 25 C AVDD 2 5V AVSS 2 5V fCLK 4 096MHz VREFP 2 5V VREFN 2 5V DVDD 3 3V PGA 1 CAPN CAPP 10nF and fDATA 1000SPS unless otherwise ...

Page 9: ...ower Supply Rejection dB 1k 10k 1M 100k DVDD AVSS AVDD 10 100 Input Frequency Hz 130 120 110 100 90 80 70 Common Mode Rejection dB 1k 10k 1M 100k ADS1282 www ti com SBAS418I SEPTEMBER 2007 REVISED MARCH 2015 Typical Characteristics continued At 25 C AVDD 2 5V AVSS 2 5V fCLK 4 096MHz VREFP 2 5V VREFN 2 5V DVDD 3 3V PGA 1 CAPN CAPP 10nF and fDATA 1000SPS unless otherwise noted Figure 13 CMR vs Input...

Page 10: ...6 4 2 0 Occurrences 1 0 0 9 0 3 0 8 0 7 0 6 25 Units 0 4 0 5 1 0 1 5 f MHz CLK 30 25 20 15 10 5 0 Power mW 2 0 2 5 4 5 3 0 3 5 4 0 100 80 Offset V m 30 25 20 15 10 5 0 Occurrences 60 40 100 20 0 20 25 Units PGA 8 PGA 1 80 60 40 ADS1282 SBAS418I SEPTEMBER 2007 REVISED MARCH 2015 www ti com Typical Characteristics continued At 25 C AVDD 2 5V AVSS 2 5V fCLK 4 096MHz VREFP 2 5V VREFN 2 5V DVDD 3 3V PG...

Page 11: ...d to the 5nV Hz The PGA is controlled by register settings conversion rate allowing gains of 1 to 64 The RESET input resets the register settings and The inherently stable fourth order delta sigma also restarts the conversion process The PWDN modulator measures the differential input signal input sets the device into a micro power state Note VIN AINP AINN PGA against the differential that register...

Page 12: ...282H The H version of the ADS1282 has an improved input stage compared to the base version ADS1282 The where ADS1282H design is optimized for use with high impedance sensors such as hydrophones The FSRRMS Full scale range RMS VREF 2 2 ADS1282H is recommended when interfacing to PGA hydrophone sensors and can also be used for low NRMS Noise RMS input referred 1 impedance geophone sensors as well Th...

Page 13: ...uts shorted Also overdriving one unused input may affect the 100 S6 S7 to AINN2 common mode test conversions of the other input If overdriven inputs are possible it is recommended to clamp the signal The typical on resistance RON of the multiplexer with external Schottky diodes switch is 30Ω When the multiplexer is used to drive an external load on one input by a signal generator on the other inpu...

Page 14: ...9 amplifiers A1 and A2 are chopped to remove the offset offset drift and the 1 f noise Chopping moves the effects to fCLK 128 8kHz which is safely out of the passband Chopping can be disabled by setting the CHOP register bit 0 When Figure 30 PGA Noise chopping is disabled the input impedance of the PGA increases substantially 100GΩ As shown in Figure 30 chopping maintains flat noise density if The...

Page 15: ...the PCM input signal applied 10 duty cycle with the negative 0 and 1 densities are nearly equal At the two full scale signal If the input is overdriven past 90 extremes of the analog input levels FS and FS modulation but below 100 modulation 10 and the 1 density of the PCM streams is approximately 0 for negative overdrive respectively the 90 and 10 respectively modulator remains stable and continu...

Page 16: ...e rate of fMOD 2 yielding internal diodes begin to conduct and the signal on the the MFLAG output The minimum MFLAG pulse width input is clipped When the input overdrive is removed is fMOD 2 the diodes recover quickly Keep in mind that the input current must be limited to 100mA peak or 10mA continuous if an overvoltage condition is possible 9 10 Modulator Input Impedance The modulator samples the ...

Page 17: ...ed of three signals tSAMPLE 1 fMOD Note that the effective impedance one output for the modulator clock MCLK and two of the reference inputs loads the external reference outputs for the modulator data M0 and M1 The modulator clock output rate is fMOD fCLK 4 Synchronization resets the MCLK phase as shown in Figure 35 The SYNC input is latched on the rising edge of CLK The MCLK resets and the next r...

Page 18: ...achieve full performance See the parallel data The decimation rate affects the overall Application Information section for reference data rate of the converter it is set by the DR 2 0 recommendations register bits as shown in Table 6 9 14 Digital Filter Equation 7 shows the scaled Z domain transfer function of the sinc filter The digital filter receives the modulator output and decimates the data ...

Page 19: ...r 9 14 2 FIR Stage The second stage of the ADS1282 digital filter is an FIR low pass filter Data are supplied to this stage from the sinc filter The FIR stage is segmented into four sub stages as shown in Figure 40 The first two sub stages are half band filters with decimation ratios of 2 The third sub stage decimates by 4 and the fourth sub stage decimates by 2 The overall decimation of the FIR s...

Page 20: ... selectable linear or minimum phase response The passband transition band and stop band responses of the filters are nearly identical but differ in the respective phase responses 9 15 1 Linear Phase Response Linear phase filters exhibit constant delay time versus input frequency that is constant group delay Linear phase filters have the property that the time delay from any instant of the input si...

Page 21: ...as shown in Figure 44 The filter phase is selected by components below the cut off frequency The transfer the PHS bit as Table 8 shows function for the filter is shown in Equation 14 of the Appendix The high pass corner frequency is programmed by registers HPF 1 0 in hexadecimal Equation 9 is used to set the high pass corner frequency Table 9 lists example values for the high pass filter 9 Where H...

Page 22: ... source Make sure to avoid excess ringing on the clock input keep the clock trace as short as possible and use a 50Ω series resistor close to the source 9 17 Synchronization Sync Pin and Sync Command The ADS1282 can be synchronized to an external event as well as synchronized to other ADS1282 devices if the sync event is applied simultaneously The ADS1282 has two sources for synchronization the SY...

Page 23: ...utput is held low until data are ready 63 Timing with Single Sync DRDY periods later When the conversion data are non zero new conversion data are ready as shown in Figure 47 When a continuous clock is applied to the SYNC pin the period must be an integral multiple of the output data rate or the device re synchronizes Note that synchronization results in the restarting of the digital filter and an...

Page 24: ...equence of the ADS1282 The power supplies can be sequenced in any order The supplies the Figure 49 Reset Timing difference of AVDD AVSS and DVDD generate an internal reset whose outputs are summed to generate a global internal reset After the supplies Table 11 Reset Timing for Figure 49 have crossed the minimum thresholds 216 fCLK cycles are counted before releasing the internal reset After PARAME...

Page 25: ...cles data transfer or commands in progress terminate and the SPI interface resets The next SCLK pulse starts a new communication cycle This timeout feature can be used to recover the interface when a transmission Figure 52 DVDD Power is interrupted or SCLK inadvertently glitches SCLK should remain low when not active 9 24 Serial Interface 9 24 2 Data Input DIN A serial interface is used to read th...

Page 26: ...de the reading data by the command mode the read output data are scaled by 1 2 operation can overlap the occurrence of the next DRDY without data corruption Table 13 Ideal Output Code Versus Input Signal INPUT SIGNAL VIN 32 BIT IDEAL OUTPUT AINP AINN CODE 1 SINC FIR FILTER FILTER 2 7FFFFFFFh 3 7FFFFFFEh 3FFFFFFFh Figure 54 DRDY with Data Retrieval 00000002h 00000001h DRDY resets high on the first ...

Page 27: ...ng that new data are available the Command mode a read data command must be sent MSB of data appears on DOUT as shown in to the device for each data conversion as shown in Figure 56 The data are normally read on the rising Figure 57 When the read data command is received edge of SCLK at the occurrence of the first falling on the eighth SCLK rising edge data are available edge of SCLK DRDY returns ...

Page 28: ...ster OFC and then multiplied by the full scale register FSC When ready to make a measurement issue the Equation 10 shows the scaling WAKEUP command Monitor DRDY when it goes low the fully settled conversion data are ready and may be read directly in Read Data Continuous mode Afterwards issue another STANDBY command 10 When ready for the next measurement repeat the The values of the offset and full...

Page 29: ...ove 1 default value Note that while the offset calibration gain correction 1 the full scale range of the register value can correct offsets ranging from FS to analog inputs should not exceed 103 to avoid input FS as shown in Table 16 to avoid input overload overload the analog inputs cannot exceed the full scale range Table 17 Full Scale Calibration Register Values Table 16 Offset Calibration Valu...

Page 30: ...ad or written During offset Figure 60 shows the calibration command sequence calibration the full scale correction is bypassed After the analog input voltage and reference have stabilized send the Stop Data Continuous command 9 29 2 GANCAL Command followed by the SYNC and Read Data Continuous The GANCAL command performs a gain calibration commands 64 data periods later DRDY goes low Before sending...

Page 31: ... output code is based on 31 bit output data 1 Set the OFSCAL 2 0 register 0h and GANCAL 2 0 400000h These values set the offset and gain registers to 0 and 1 respectively 11 2 Apply a zero differential input to the input of the system Wait for the system to settle and then For ac signal calibration use an RMS value of average n output readings Higher numbers of collected data as shown in Equation ...

Page 32: ...61 1 tSCLKDLY 24 fCLK min Figure 61 Consecutive Commands Table 20 Command Descriptions COMMAND TYPE DESCRIPTION 1st COMMAND BYTE 1 2 2nd COMMAND BYTE 3 WAKEUP Control Wake up from Standby mode 0000 000X 00h or 01h STANDBY Control Enter Standby mode 0000 001X 02h or 03h SYNC Control Synchronize the A D conversion 0000 010X 04h or 5h RESET Control Reset registers to default values 0000 011X 06h or 0...

Page 33: ... the 16th falling edge of SCLK the register data appear on DOUT Figure 62 Standby Command Sequence The RREG command is illustrated in Figure 63 Note that a delay of 24 fCLK cycles is required between SYNC Synchronize the A D Conversion each byte transaction Description This command synchronizes the WREG Write to Register analog to digital A D conversion Upon receipt of the command the reading in p...

Page 34: ...on Description This command performs an offset Description This command performs a gain calibration The inputs to the converter or the inputs calibration The inputs to the converter should have a to the external pre amplifier should be zeroed and stable dc input typically full scale but not to exceed allowed to stabilize before sending this command 103 full scale The gain calibration register upda...

Page 35: ...S FILTR1 FILTR0 02h CONFIG1 08h 0 MUX2 MUX1 MUX0 CHOP PGA2 PGA1 PGA0 03h HPF0 32h HPF07 HPF06 HPF05 HPF04 HPF03 HPF02 HPF01 HPF00 04h HPF1 03h HPF15 HPF14 HPF13 HPF12 HPF11 HPF10 HPF09 HPF08 05h OFC0 00h OFC07 OFC06 OFC05 OFC04 OFC03 OFC02 OFC01 OFC00 06h OFC1 00h OFC15 OFC14 OFC13 OFC12 OFC11 OFC10 OFC09 OFC08 07h OFC2 00h OFC23 OFC22 OFC21 OFC20 OFC19 OFC18 OFC17 OFC16 08h FSC0 00h FSC07 FSC06 F...

Page 36: ...ite 1 Bit 5 3 Data Rate Select DR 2 0 000 250SPS 001 500SPS 010 1000SPS default 011 2000SPS 100 4000SPS Bit 2 FIR Phase Response PHASE 0 Linear phase default 1 Minimum phase Bit 1 0 Digital Filter Select FILTR 1 0 Digital filter configuration 00 On chip filter bypassed modulator output mode 01 Sinc filter block only 10 Sinc LPF filter blocks default 11 Sinc LPF HPF filter blocks 36 Submit Document...

Page 37: ... AINP1 and AINN1 default 001 AINP2 and AINN2 010 Internal short via 400Ω 011 AINP1 and AINN1 connected to AINP2 and AINN2 100 External short to AINN2 Bit 3 PGA Chopping Enable CHOP 0 PGA chopping disabled 1 PGA chopping enabled default Bit 2 0 PGA Gain Select PGA 2 0 000 G 1 default 001 G 2 010 G 4 011 G 8 100 G 16 101 G 32 110 G 64 Copyright 2007 2015 Texas Instruments Incorporated Submit Documen...

Page 38: ...h Table 29 OFC1 Offset Calibration Mid Byte Address 06h 7 6 5 4 3 2 1 0 OC15 OC14 OC13 OC12 OC11 OC10 OC09 OC08 Reset value 00h Table 30 OFC2 Offset Calibration High Byte Address 07h 7 6 5 4 3 2 1 0 OC23 OC22 OC21 OC20 OC19 OC18 OC17 OC16 Reset value 00h FSC2 FSC1 FSC0 These three bytes set the full scale calibration value Table 31 FSC0 Full Scale Calibration Low Byte Address 08h 7 6 5 4 3 2 1 0 F...

Page 39: ...rsions take SYNC when in Read Data Continuous mode hold SCLK low and then high low for 64 DRDY periods 6 Read data If the Read Data Continuous mode is 2 Configure the registers The registers are active the data are read directly after DRDY falls configured by either writing to them individually or by applying SCLK pulses If the Read Data as a group Software may be configured in either Continuous m...

Page 40: ...The REF5045 reference has supply the advantage of operating from the 5V power The geophone input signal is filtered both supply The REF5050 requires 5 2V minimum power differentially by components C4 and R1 to R4 and supply filtered independently by components C2 C3 and R1 Optional components R8 and R9 provides a 20mV R2 The differential filter removes high frequency offset to the ADS1282 The inte...

Page 41: ... Test Source 21 22 18 17 16 15 13 14 6 12 25 27 R 20k 5 W R 20k 6 W 19 20 R 1 9 75kW R 75kW 8 1 C 1nF C0G 2 1 F m 2 5V 2 5V 2 5V 2 ADS1282 www ti com SBAS418I SEPTEMBER 2007 REVISED MARCH 2015 1 Optional 20mV offset Match to 0 1 to maintain CMR 2 Optional external diode clamps Figure 65 Geophone Interface Application Copyright 2007 2015 Texas Instruments Incorporated Submit Documentation Feedback ...

Page 42: ...tors in series with the DRDY output from each ADS1282 can be used digital traces can help to reduce ringing by controlling however when the devices are synchronized the impedances Place the resistors at the source driver DRDY output from only one device is sufficient A end of the trace Unused digital inputs should not shared SCLK line between the devices is optional float tie them to DVDD or GND T...

Page 43: ...15 293598 9668991 61387 16314388 b16 987253 327749 7546 1518875 b17 2635779 7171917 94192 12979500 b18 3860322 10926627 50629 11506007 b19 3572512 10379094 101135 2769794 b20 822573 6505618 134826 12195551 b21 4669054 1333678 56626 6103823 b22 12153698 2972773 220104 6709466 b23 19911100 5006366 56082 9882714 b24 25779390 4566808 263758 353347 b25 27966862 2505652 231231 8629331 b26 25779390 12633...

Page 44: ... 9818477 1497356 b53 41426374 168417 b54 56835776 1166800 b55 41426374 644405 b56 9818477 675082 b57 10537298 806095 b58 8538057 211391 b59 2950811 740896 b60 6661730 141976 b61 641555 527673 b62 4511116 327618 b63 2338095 278227 b64 2425494 363809 b65 2811738 70646 b66 688945 304819 b67 2490395 63159 b68 522533 205798 b69 1741565 124363 b70 1162189 107173 b71 878642 131357 b72 1300087 31104 b73 1...

Page 45: ...2 1 8388608 PHASE MINIMUM PHASE PHASE MINIMUM PHASE b88 134826 732 b89 101135 4687 b90 50629 976 b91 94192 2551 b92 7546 1339 b93 61387 1103 b94 33460 1085 b95 25549 314 b96 34123 681 b97 348 16 b98 22008 349 b99 10620 96 b100 8280 144 b101 10663 78 b102 266 46 b103 7419 42 b104 6692 9 b105 2481 16 b106 75 0 b107 432 4 b108 132 0 b109 0 0 Copyright 2007 2015 Texas Instruments Incorporated Submit D...

Page 46: ...ed as shown in Equation 15 15 Table 35 tDR Time for Data Ready Sinc Filter fDATA fCLK 1 128k 440 64k 616 32k 968 16k 1672 8k 2824 1 For SYNC and Wake Up commands fCLK number of CLK cycles from next rising CLK edge directly after eighth rising SCLK edge to DRDY falling edge For Wake Up command only subtract two fCLK cycles Table 35 is referenced by Table 10 and Table 12 46 Submit Documentation Feed...

Page 47: ...pical specification in Digital Filter Response Minimum phase filter settling time in Electrical Characteristics table 4 Corrected units typo of Figure 41 20 Moved Equation 14 and Equation 15 to the Appendix from the HPF Stage section 21 Added footnote 2 to Table 13 Ideal Output Code 26 Corrected sign typo in Equation 13 46 Changes from Revision E October 2008 to Revision F Page Added tCMD specific...

Page 48: ...ble for use in specified lead free processes TI may reference these types of products as Pb Free RoHS Exempt TI defines RoHS Exempt to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption Green TI defines Green to mean the content of Chlorine Cl and Bromine Br based flame retardants meet JS709B low halogen requirements of 1000ppm threshold Antimon...

Page 49: ...certain information to be proprietary and thus CAS numbers and other limited information may not be available for release In no event shall TI s liability arising out of such information exceed the total purchase price of the TI part s at issue in this document sold by TI to Customer on an annual basis OTHER QUALIFIED VERSIONS OF ADS1282 Space ADS1282 SP NOTE Qualified Version Definitions Space Ra...

Page 50: ...ins SPQ Reel Diameter mm Reel Width W1 mm A0 mm B0 mm K0 mm P1 mm W mm Pin1 Quadrant ADS1282HIPWR TSSOP PW 28 2000 330 0 16 4 6 9 10 2 1 8 12 0 16 0 Q1 ADS1282IPWR TSSOP PW 28 2000 330 0 16 4 6 9 10 2 1 8 12 0 16 0 Q1 PACKAGE MATERIALS INFORMATION www ti com 26 Feb 2019 Pack Materials Page 1 ...

Page 51: ... Package Type Package Drawing Pins SPQ Length mm Width mm Height mm ADS1282HIPWR TSSOP PW 28 2000 350 0 350 0 43 0 ADS1282IPWR TSSOP PW 28 2000 350 0 350 0 43 0 PACKAGE MATERIALS INFORMATION www ti com 26 Feb 2019 Pack Materials Page 2 ...

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Page 54: ...se resources are subject to change without notice TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource Other reproduction and display of these resources is prohibited No license is granted to any other TI intellectual property right or to any third party intellectual property right TI disclaims responsibility for...

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