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2.6 External Voltage Reference
shows a reference buffer that allows connection of an external voltage reference to connector J5.
This circuit and connection is not required if the onboard voltage reference is used (see
). The
amplifier here was selected for low voltage offset and low offset drift. The amplifier topology is designed to drive
capacitive loads. For information on this topology, see the
Op Amp Stability Videos in TI Precision Labs
.
1.00k
R24
0R35
DNP
REFP
1.00k
R46
0R56
DNP
REFN
GND
1.00k
R36
1.00k
R58
EXTERNAL REFERENCE
1
2
3
4
5
OPA192IDBVR
U6
1
2
3
4
5
OPA192IDBVR
U4
VP
0R52
DNP
VM
0R60
DNP
VP
0R30
DNP
VM
0R42
DNP
0R29
AVDD1
AVSS
0R41
0R51
AVDD1
0R59
AVSS
AVSS
AVSS
AVSS
AVSS
AVSS
AVSS
AVSS
AVSS
100nF
C21
100nF
C27
100nF
C37
100nF
C41
0
R23
DNP
0
R45
DNP
REFPb
REFNb
REFPb
REFNb
1
2
3
J5
0393570003
10µF
C39
37.4
R55
0.033µF
C35
10.0k
R49
1µF
16V
C40
1µF
16V
C25
10µF
C24
37.4
R34
0.033µF
C19
10.0k
R25
Figure 2-5. External Reference Connection and Buffer
EVM Analog Interface
8
ADS127L11EVM-PDK Evaluation Module
SBAU351 – APRIL 2021
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