Texas Instruments ADS1259EVM, User Manual

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Evaluating Performance with the ADCPro Software
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10.1.3 ADC Configuration Tab
The first tab for the ADS1259EVM is the ADC Configuration Tab. This set of controls is used primarily for
setting up the operation for the ADS1259. This tab is broken up into three subsections. The ADC
Configuration tab is shown in
Figure 32 .
Figure 32. ADC Configuration Tab
The first subsection is Clock Options. This set of controls is used primarily for monitoring and setting
different clock and filter options. First, two indicator lights show the clock source for the ADC, showing if
the master clock source is generated from the internal oscillator, or from some external source. The clock
source indicator is shown at the start up of the plug-in. It can be re-read with the Update button.
A push button labeled SYNCOUT allows for a divided modulator clock to be put onto the SYNCOUT pin of
the ADS1259. This can be used to drive the input chopping of the PGA280. To synchronize the two
devices, the PGA280 must be set to External (as shown in the PGA-Config tab under the Sync pull-down;
see
Figure 34 ) and connected through pins 2 and 3 of J1 on the ADS1259EVM.
There are two different digital filter options for the ADS1259. A fixed decimation sinc5 filter is then followed
by either a sinc1 filter or a sinc2 filter that is selected by the pull-down menu labeled Filter.
The second subsection is used to control the reference. The ADC reference source can be selected here
to be either the internal, onboard reference of the ADS1259 or the external reference seen on VREFP and
VREFN. The VREF voltage is adjusted here for readings for plug-in tools.
In order to use the internal reference, it must be enabled with the Internal Reference Enable button.
The final subsection of the ADC Configuration tab is Power Options. With the ADS1259, conversions can
be initiated by the rising edge of START. The pull-down menu labeled Start Delay, will delay the part
coming out of startup to allow external circuitry to settle before a conversion is started. The pull-down
menu can be used to set the delay to a fixed time as a function of the master clock period. While this
function is not useful in reading out data from the device, it is observable by using one of the PGA280
GPIO pins to toggle the START pin of the ADS1259. Afterward, the delay of the DRDY pin can be seen.
28 ADS1259EVM, ADS1259EVM-PDK SBAU163A – March 2010 – Revised April 2010
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