Texas Instruments ADC31JB68, User Manual, Page: 13 / 20

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Alternate Hardware Configurations
13 SLAU630A – August 2015 – Revised August 2016
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ADC31JB68 Evaluation Module
5 Alternate Hardware Configurations
This section describes alternate hardware configurations that can be used for customized evaluation.
5.1 Clocking Options
By default, the ADC requires a clock source from an external signal generator. Optionally, the EVM may
be configured such that the ADC is provided a clock signal by the LMK04828 in a variety of options.
These options are described in the following sections.
5.1.1 Providing the ADC Sampling Clock From the LMK04828
The EVM may be reconfigured to route a clock from the LMK04828 to the ADC31JB68 to be used as the
device clock. This configuration represents a more realistic system configuration but the data conversion
noise performance is affected by the noise of the clock signal from the LMK device. The EVM must be
changed from the default configuration in the following ways:
• Remove R40, R41
• Place R43 and R50 with 0402, 0- Ω resistors
• Remove R234
• Configure the LMK04828 to output an LVPECL clock on the DCLKout2 output
5.1.2 Recommended LMK04828 Configurations
The LMK04828 can be used in a number of useful configurations to provide the necessary clocks for the
ADC and JESD204B interface as described in
Table 6 :
Table 6. Recommended LMK04828 Configurations
Mode Description
Clock Distribution Mode Input reference is distributed to clock outputs and the frequency is divided, if desired. Frequency
multiplication not supported. Input reference must be provided to CLKin1 input via CLK SMA
connector and R21 or via EXTREF SMA connector using an external signal generator.
Clock Multiplier Mode (PLL2
Only) Input reference is locked to internal VCO, allowing frequency Integer-N multiplication from input to
output. Reference must be provided at OSCin input via EXTREF SMA connector or on-board XO
at Y3.
Jitter Cleaner and
Clock Multiplier Mode
(PLL1 + PLL2) Input reference is cleaned with very low bandwidth PLL1 and then multiplied to the desired
frequency using PLL2. Reference must be provided at CLKin1 input or on-board XO at Y1/Y2.
On-board VCXO at Y3 is also required.