Texas Instruments 296-38528-ND, User Manual

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SDI
SCLK
SDO
CONVST
JP2
1
2
3
JP3 (CLOSED)
DVDD
10 k
CONVST (J2:17) CONVST
CS
CS ( J2:1 or J2:7 )
SDI
SCLK
SDO
CONVST
JP2
2
3
JP3 (OPEN)
DVDD
10 k
J2:17
CS ( J2:1 or J2:7 )
CS
EVM Digital Configuration
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5 EVM Digital Configuration
The EVM offers two jumpers (JP2 and JP3) to configure the EVM in either 3-wire SPI mode or 4-wire SPI
mode.
5.1 SPI 3-Wire Mode (JP2:2–3 and JP3:OPEN)
This mode is used to communicate with the MMB0 motherboard. Use the chip-select signal to bring the
ADS8339 digital output out of tri-state mode and initialize conversions. The rising edge of the chip-select
signal starts a conversion, and after the conversion time, the falling edge of the chip-select signal brings
the digital output out of tri-state mode.
Figure 4 shows the serial configuration for this mode.
Figure 4. Serial 3-Wire Configuration
5.2 SPI 4-Wire Mode (JP2:1–2 and JP3:CLOSED)
The chip-select signal is used to bring the ADS8339 digital output out of tri-state. However, conversion is
initialized from J3:17 as an independent signal. The rising edge of J3:17 (CONVST) starts a conversion,
and after the conversion time, the falling edge of the chip-select signal brings the digital output out of tri-
state.
Figure 5 shows the serial configuration for this mode.
Figure 5. Serial 4-Wire Configuration
8 ADS8339EVM-PDK SBAU233A – October 2014 – Revised November 2015
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