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Tews Technologies TPMC467-10R, User Manual

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Tews Technologies TPMC467-10R User Manual Download Page 23

 

5.4 RS485/RS422 Configuration Examples 

5.4.1  RS422 Multidrop 

RS485 

HDPLX 

RENA 

RTERM 

TTERM 

FCTR[5] 

ON 

OFF 

OFF 

ON* 

OFF 

OFF 

     

 

* Terminate only if the device is a receiver and the end-point of the bus. 

 

D

ZT

R

R

R

 

Figure 5-4 :  RS422 Multidrop Configuration 

5.4.2  RS422 Full Duplex Point to Point 

RS485 

HDPLX 

RENA 

RTERM 

TTERM 

FCTR[5] 

ON 

OFF 

OFF 

ON 

OFF 

OFF 

D

ZT

R

R

ZT

D

 

Figure 5-5:  RS422 Full Duplex Point to Point Configuration 

5.4.3  RS485 Full Duplex Point to Point 

RS485 

HDPLX 

RENA 

RTERM 

TTERM 

FCTR[5] 

ON 

OFF 

OFF 

ON 

ON 

OFF 

D

ZT

R

R

ZT

D

ZT

ZT

 

Figure 5-6:  RS485 Full Duplex Point to Point Configuration 

 

TPMC467 User Manual Issue 1.0.4 

Page 23 of 30 

Summary of Contents for TPMC467-10R

Page 1: ...nel RS232 RS422 RS485 Programmable Serial Interface Version 1 0 User Manual Issue 1 0 4 August 2014 TEWS TECHNOLOGIES GmbH Am Bahnhof 7 25469 Halstenbek Germany Phone 49 0 4101 4058 0 Fax 49 0 4101 40...

Page 2: ...rves the right to change the product described in this document at any time without notice TEWS TECHNOLOGIES GmbH is not liable for any damage arising out of the application or use of the device descr...

Page 3: ...006 1 1 New address TEWS LLC September 2006 1 2 Technical Specification update January 2007 1 0 3 New notation for HW Engineering Documentation Releases December 2009 1 0 4 General Revision August 201...

Page 4: ...21 5 3 1 1 Auto RS485 Operation 21 5 3 1 2 RS485 Receiver Control 21 5 3 1 3 Slew Rate Limiting 22 5 3 1 4 Low Power Shutdown 22 5 3 2 Channel Setup 22 5 4 RS485 RS422 Configuration Examples 23 5 4 1...

Page 5: ...E 3 1 XR17D154 LOCAL SPACE CONFIGURATION 9 TABLE 3 2 DEVICE CONFIGURATION SPACE 9 TABLE 3 3 UART REGISTER SET OFFSET 10 TABLE 3 4 UART REGISTER SET 10 TABLE 3 5 DEVICE CONFIGURATION REGISTERS 11 TABLE...

Page 6: ...and GND RS422 and RS485 full duplex support a four wire interface RX RX TX TX plus ground GND RS485 half duplex supports a two wire interface DX DX plus ground GND Each channel has 64 byte transmit an...

Page 7: ...RxD GND RS485 Half Duplex Dx GND Termination Software selectable 120 Programmable Baud Rates RS232 up to 921 6 kbps RS422 up to 5 5296 Mbps ESD Protection 15kV Human Body Model I O Connector 4x RJ45 M...

Page 8: ...Environment GB 20 C The MTBF calculation is based on component FIT rates provided by the component suppliers If FIT rates are not available MIL HDBK 217F and MIL HDBK 217F Notice 2 formulas are used...

Page 9: ...Device Configuration Space Content PCI Address Size Bit UART 0 Register Set PCI Base Address 0 0x0000 to 0x007F 32 Device Configuration Registers PCI Base Address 0 0x0080 to 0x009F 32 UART 0 Register...

Page 10: ...ata Width 0x000 0x00F UART Channel Configuration Registers First 8 registers are 16550 compatible R W 8 16 32 0x010 0x07F Reserved 0x080 0x093 Channel 0 Device Configuration Registers All other channe...

Page 11: ...0 0x086 TIMERLSB Programmable Timer Value R W 0x00 0x087 TIMERMSB R W 0x00 0x088 8XMODE Sampling Rate Select R W 0x00 0x089 REGA Reserved 0x00 0x08A RESET UART Reset W 0x00 0x08B SLEEP UART Sleep Mode...

Page 12: ...r R 0x01 W 0x00 0x03 LCR Line Control Register R W 0x00 0x04 MCR Modem Control Register R W 0x00 0x05 LSR Line Status Register Reserved R 0x60 W 0x06 MSR Modem Status Register MSR Auto RS485 Delay not...

Page 13: ...ple The address for the LCR register of UART channel 2 is PCI Base Address PCI Base Address for the Device Configuration Space 0x0400 Offset of the UART register set for serial channel 2 0x0003 Offset...

Page 14: ...er 0 Unimplemented N 00000000 0x1C Base Address Register 1 Unimplemented N 00000000 0x20 Base Address Register 2 Unimplemented N 00000000 0x24 Base Address Register 3 Unimplemented N 00000000 0x28 Res...

Page 15: ...2C s b Table 4 2 Configuration EEPROM TPMC467 xx Subsystem ID Value Offset 0x0C TPMC467 10R 0x000A TPMC467 11R 0x000B The words following the configuration data contain The module version and revision...

Page 16: ...Max Data Rate RS422 high 0x0098 0x0098 0x23 Max Data Rate RS422 low 0x9680 0x9680 0x24 Max Data Rate TTL high 0x0000 0x0000 0x25 Max Data Rate TTL low 0x0000 0x0000 0x26 Max Data Rate RS485 Full Duple...

Page 17: ...2 7 011 Control Register Channel 3 7 Table 5 1 CPLD Register Address Map 5 1 2 Channel Control Register This register is identical for all channels Bit Symbol Description Access Reset Value 6 SHDN Ac...

Page 18: ...level high operates as RS232 with a logic level low 0 RS232 1 RS485 R W 0 Table 5 2 Channel Control Register 5 2 CPLD Access The CPLD it is connected to the MPIO pins of the XR17D154 to provide acces...

Page 19: ...5 2 2 CPLD Bus Protocol 5 2 2 1 Write A CPLD register write access starts with setting CEN to 1 This resets the CPLD s internal state machine Before the first clock pulse is issued ADR and DATAOUT hav...

Page 20: ...nal state machine Before the first clock pulse is issued ADR and R W have to be set The first rising edge of CLK samples the ADR bits and starts the output of the first DATAIN bit ADR determines which...

Page 21: ...5 3 1 Special Features 5 3 1 1 Auto RS485 Operation In RS485 half duplex applications it is necessary to tristate the driver when it is not active The XR17D154 provides a special function the Auto RS4...

Page 22: ...485 RS422 mode 5 3 2 Channel Setup Each interface channel must be set up in its associated Channel Control Register in the CPLD Depending on the interface configuration the Auto RS485 Operation must b...

Page 23: ...22 Multidrop Configuration 5 4 2 RS422 Full Duplex Point to Point RS485 HDPLX RENA RTERM TTERM FCTR 5 ON OFF OFF ON OFF OFF D ZT R R ZT D Figure 5 5 RS422 Full Duplex Point to Point Configuration 5 4...

Page 24: ...plex Multi point Also referred to as party line Master RS485 HDPLX RENA RTERM TTERM FCTR 5 ON OFF OFF ON ON OFF Slave RS485 HDPLX RENA RTERM TTERM FCTR 5 ON OFF OFF ON ON ON Terminate only if the devi...

Page 25: ...eivers convert RS232 signals to CMOS logic output levels All receivers have inverting outputs that remain active in shutdown The MAX3161E permit their receiver inputs to be driven to 25V Floating rece...

Page 26: ...he termination is software selectable 5 6 Block Diagram XR17D154 RS232 TxD RTS RxD CTS TxD TxD Dx RTS RxD RxD TxD Dx CTS RxD 1 RS485 RS232 RS485 Duplex RENA SLEWLIMIT SHDN HDPLX RS232 RS485 RTERM TTRE...

Page 27: ...00 150 0x1200 0x12 0x00 1200 300 0x0900 0x09 0x00 2400 600 0x0480 0x04 0x80 4800 1200 0x0240 0x02 0x40 9600 2400 0x0120 0x01 0x20 19 2k 4800 0x0090 0x00 0x90 38 4k 9600 0x0048 0x00 0x48 57 6k 14 4k 0x...

Page 28: ...These steps should be used to modify MCR register bit 7 of an UART channel set baud rate generator prescaler 1 Set UART channel EFR register bit 4 to 1 enable modification of MCR register bits 5 7 2 M...

Page 29: ...7 CTS RxD 8 RTS RxD Table 7 1 Pin Assignment RJ45 Front Panel I O Connector The RS232 pinout is compliant to TIA EIA 561 EIA 232D 7 2 Front Panel I O Connector TPMC467 11R Pin Signal RS232 Signal RS4...

Page 30: ...0 3 are mapped onto the 4 front panel connectors labeled Port1 Port4 Serial Channel Front Panel Port Channel 0 Port 1 Channel 1 Port 2 Channel 2 Port 3 Channel 3 Port 4 Table 7 3 Serial Channel to Fro...

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