5 Configuration Hints
The TPMC467 physical interfaces of the serial channels are individually software programmable to
various interface configurations. For this purpose a CPLD provides a control register for each interface
channel.
5.1 CPLD Description
The CPLD provides a Channel Control Register for each of the interface channels. Each of the
Channel Control Registers is individually addressable. The access to this registers is described in
detail in chapter “5.2 CPLD Access”.
5.1.1 CPLD Address Map
Refer to the following chart for the register addresses.
Address
Register Name
Size (Bit)
000
Control Register Channel 0
7
001
Control Register Channel 1
7
010
Control Register Channel 2
7
011
Control Register Channel 3
7
Table 5-1 : CPLD Register Address Map
5.1.2 Channel Control Register
This register is identical for all channels.
Bit
Symbol
Description
Access
Reset
Value
6
SHDN
Active-Low Shutdown-Control. Drive SHDN high to shut down
transmitters and charge pump.
‘0’: Normal operation
‘1’: Shutdown
R/W
1
5
SLEW
LIMIT
Transmitter Speed-Select. Select slew-rate limiting for RS232
and RS485. Slew-rate limits with a logic-level high.
‘0’: Normal data rate limit (RS232: 1 Mbps; RS485: 10 Mbps)
‘1’: Limit data rate to 250 kbps (both RS232 & RS485)
R/W
0
4
TTERM
Transmitter Termination Enable
Terminate transmit line with a 120
Ω termination resistor
‘0’: Termination inactive
‘1’: Termination active
R/W
0
3
RTERM
Receiver Termination Enable
Terminate receive line with a 120
Ω termination resistor
‘0’: Termination inactive
‘1’: Termination active
R/W
0
TPMC467 User Manual Issue 1.0.4
Page 17 of 30
