TCP201 User Manual Issue 1.4
Page 21 of 35
4 IP Interface
The IP FPGA provides the interface between the PCI9030 local bus and the IP slots.
The IP FPGA also provides the IP Interface Control Registers.
A PCI access to the TCP201 will be terminated in every case. If the IP does not generate an ACK#, a
local timeout will terminate the IP access after a timeout time of 8µs and the timeout bit is set in the IP
Status Register. All F’s are returned for read cycles.
The IP FPGA is configured at power-up by an on board serial PROM.
4.1 PCI9030 Local Space Assignment
The PCI9030 local spaces must be used to access the IP Interface. The PCI base address for each
local space can be obtained from the PCI9030 PCI configuration register space.
Space 0 contains the IP Control and Status Register.
Space 1 provides access to I/O ID and INT Space of all IPs.
Space 2 is used for the IP A-D Memory space.
Space 3 is also used for IP A-D Memory space, but provides linear addressing for IP modules, that
use only D7:0.
PCI9030
Local Space
Size
(Byte)
Port Width
(Bit)
Endian Mode
IP Interface Space
0
256
16
Little
IP Interface Register
1
1K
16
Little
IP A-D ID, INT, I/O Space
2
32M
16
Little
IP A-D MEM Space (16 bit)
3
16M
8
Little
IP A-D MEM Space (8 bit)
Figure 4-1 : PCI9030 Local Space Assignment
