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5. IP Addressing
The TIP850 is controlled by a set of registers, which are directly accessible in the IO address space of the IP.
ADDRESS
NAME
FUNCTION
SIZE
$ 00
ADCCSR
ADC Control and Status Register
word
$ 02
ADCCON
ADC Convert Register
word
$ 04
ADCDAT
ADC Data Register
word
$ 06
DACDA1
DAC 1 Data Register
word
$ 08
DACDA2
DAC 2 Data Register
word
$ 0A
DACDA3
DAC 3 Data Register
word
$ 0C
DACDA4
DAC 4 Data Register
word
$ 0E
DACLOA
DAC Load Register
word
$ 41
INTVEC
Interrupt Vector Register
byte
5.1. ADC Register Set
The ADC part of the TIP850 is controlled by a set of 3 register.
5.1.1. ADC Control and Status Register
The ADC Control and Status Register ADCCSR is used to select an input channel, the gain and the mode for
the next data conversion. This is done by writing the corresponding bit pattern into bit 0 to bit 8. The status of
the ADC can be obtained by reading bit 14 and bit 15.
5.1.1.1. ADC Channel Selection
Bit 0 to bit 3 of the ADCCSR determine the input channel for the next data conversion. These bits are write only.
The write only bit 4 of the ADCCSR is controlling if the module operates in differential or in single ended mode.
If this bit is set to ’1’ differential mode is selected.
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Figure 4: ADCCSR Input Channel Selection and Mode
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Summary of Contents for TIP850
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