7,3 8VHU 0DQXDO 9HUVLRQ
5.3.2. Enable Synchronous Status Latch
If bit 2 of the Channel 1 Control Register is set to ’1’ the Channel 1 Status Register will be latched at the time
reading the Channel 1 Data Register, ensuring that the Channel 1 Status Register reflects the state at data read
time. The status will remain latched until it is read.
To use this mode of operation, bit 3 of the Channel 1 Control Register must be set to ’0’.
5.3.3. Enable Synchronous Conversion
If bit 3 is set to ’1’ the Synchronous Conversion of Channel 1 and Channel 2 is enabled.
A read access to the Channel 1 Data Register starts the conversion for channel 1 and 2, latches the Status Regi-
ster for channel 1 and 2 and provides the data for channel 1. Latching the Status Register ensures that the Status
Registers reflect the state at data read time. The status of both Status Registers will remain latched until a read
access to Channel 2 Status Register.
This bit is only active for TIP150-4X with two channel resolver-to-digital converter. For TIP150-3X this bit is don’t
care.
1RWH
$IWHU 5HVHW DOO ELWV DUH VHW WR GHIDXOW FRQGLWLRQV DUH ELW FRQYHU
VLRQ QR V\QFKURQRXV FRQYHUVLRQ
Summary of Contents for TIP150
Page 2: ... 7 3 8VHU 0DQXDO 9HUVLRQ ...
