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P52 

 

Chapter 1: Introduction 

 

1-2 

A 100M BaseT Ethernet controller (Wiznet) can be installed to provide network connectivity.  A software 
stack library is available, supporting network protocols like ARP, DHCP, UDP, ICMP, and of course TCP 
over the Ethernet network.   

Two channels of RS-232 drivers and a 5V linear regulator are on-board. An optional RS232 or RS485 
driver can be installed for the optional 3

rd

 UART of the host controller. The 

P52 

requires 8.5V to 12V DC 

power supply with linear regulator, or up to 30V DC power input with an optional switching regulator 
without generating excessive heat. 

 

 

 

TERN host  

controller 

586-Engine 

or 

A-Engine86

, 

i386-Engine

 

 

PAL 

HP2020 

Quad. 

Decoders 

P52

High speed 

parallel 

ADC 

High speed 

parallel 

DAC 

8 channels 

opto-couplers 

address, 
data bus 

CPU PIOs 

address bus

sinking/sourcing 

H.V. drivers 

100M base-T 

Ethernet 

interface 

data bus 

 

Figure 1.1 Functional block diagram of the P52 

 

1.2

 

Features

 

►

 4.4x3.1x0.5 inches.  

►

 Driven by 

586-Engine™

 ,  

i386-Engine™, A-Engine86™

. 

►

 Power consumption: < 200 mA @ 9V-12V 

►

 2 channels RS-232 serial communication 

►

 24 PPIs, 14 high voltage sourcing or sinking drivers 

►

 Wiznet 100M Base-T Ethernet Controller  

►

 8 ch. 16-bit ADC( AD7655) x 2 

►

 4 ch. 16-bit DAC (DAC8544) with buffer ops*. 

►

 8 opto-isolators and 2 quadrature decoders* 

►

 5V switching regulator*  

►

 RS-232/485 for optional 3

rd

 UART on controlling ‘Engine’* 

     

*optional 

 

Summary of Contents for P52

Page 1: ... card with ADC DAC 24 PPI I Os 100M BaseT Ethernet Quadrature Decoders RS232 485 Technical Manual 1724 Picasso Avenue Davis CA 95616 USA Tel 530 758 0180 Fax 530 758 0181 Internet Email sales tern com http www tern com ...

Page 2: ... Tel 530 758 0180 Fax 530 758 0181 Email sales tern com http www tern com Important Notice TERN is developing complex high technology integration systems These systems are integrated with software and hardware that are not 100 defect free TERN products are not designed intended authorized or warranted to be suitable for use in life support applications devices or systems or in other critical appli...

Page 3: ...AC analog output offset It also supports eight 16 bit parallel ADC inputs AD7655 The P52 can buffer PIOs with 16 sourcing drivers UDN2982 or 14 sinking drivers ULN2003 These drivers can source or sink 350 mA at 50V per line to directly drive solenoids relays or lights Eight high isolation voltage photocouplers PS2701 NEC can be installed to provide optically isolators to PIOs Two quadrature decode...

Page 4: ...rating excessive heat TERN host controller 586 Engine or A Engine86 i386 Engine PAL HP2020 Quad Decoders P52 High speed parallel ADC High speed parallel DAC 8 channels opto couplers address data bus CPU PIOs address bus sinking sourcing H V drivers 100M base T Ethernet interface data bus Figure 1 1 Functional block diagram of the P52 1 2 Features 4 4x3 1x0 5 inches Driven by 586 Engine i386 Engine...

Page 5: ... P52 via J1 and J2 headers before power on The host communicates through SER0 for debugging by default Thus the 5x2 IDC connector must be installed on the SER0 of the P52 header H2 IMPORTANT Note that the red side of the cable must point to pin 1 of the H2 header The DB9 connector should be connected to one of your PC s COM Ports COM1 or COM2 Figure 2 1 P52 driven by host controller A Engine 40 Se...

Page 6: ...P52 as shown below with the 5P as host Figure 2 2 P52 driven by host controller 586 Engine P The P52 must be powered by an unregulated 12 Volts or up to 30V with an optional switching regulator A 2x1 screw terminal is installed to accept this 12V input See schematic for orientation of screw terminal Using the power jack adapter provided with a TERN EV P or DV P Kit connect the output of the wall t...

Page 7: ...3 channels RS 232 485 drivers By default two RS 232 drivers are ready for the two asynchronous serial UARTs from the installed Engine controller via 20x2 pin header J1 and J2 One optional 3rd RS232 or RS485 driver can be installed to support the optional UART SCC2691 on the Engine controller The default debug serial port SER0 is routed at H2 SER1 at H3 and SCC port at H4 Note H4 is hidden beneath ...

Page 8: ...R U2 pin 11 ADR for ethernet 0x40 RD RDT U16 pin 1 RDT read optos 0x48 RD 0x50 HP1 HP2 U6 pin 4 U8 pin 4 read HP2020 U6 read HP2020 U8 0x60 WR 0x68 HV1 HV2 U23 pin 4 U24 pin 4 write HC259 U23 write HC259 U24 0x70 0x78 CV CV1 U15 pin 35 U22 pin 35 CV for AD7655 U15 CV1 for AD7655 U22 Table 3 1 186 Engine Mapping I O space Select Signal Location Usage 0x1080 82 84 86 PP1 U1 pin 7 PPI for PPI 0x1090 ...

Page 9: ...p u t M o d e 0 M o d e 1 G R O U P 2 P o rt 2 U p p e r P o rt 0 M o d e 0 1 0 1 0 0 0 1 O u tp u t In p u t O u tp u t In p u t M o d e 0 M o d e 1 M o d e 2 1 X C o m m a n d S e le c t 0 1 B it m a n ip u la tio n M o d e S e le c t Figure 3 1 Mode Select Command Word P52 maps U1 the PPI 8255 at base I O address PPI 0x1080 586 Engine and 0x00 186 Engine All ports registers are offsets of this ...

Page 10: ...l 16 bit ADC AD7655 Two AD7655 ADC s may be installed on the P52 The unique 16 bit parallel ADC AD7655 0 5V supports ultra high speed 1 MHz conversion rate analog signal acquisition The AD7655 contains two low noise high bandwidth track and hold amplifiers that allow simultaneous sampling on two channels Each track and hold amplifier has a multiplexer in front to provide a total of 4 channels anal...

Page 11: ...gnal will turn the coupler ON Opto coupler intputs are routed to pins J4 1 8 3 3 8 High Voltage High Current Drivers ULN2003 U13 and U14 are high voltage high current Darlington transistor arrays consisting of 7 silicon NPN Darlington pairs on a common monolithic substrate All channels feature open collector outputs for sinking 350 mA at 50V and integral protection diodes for driving inductive loa...

Page 12: ... P52 3 6 3 4 Headers and Connectors Two 20x2 0 1 spacing sockets are installed on the P52 Figure 3 3 Pin header locations J1 pin 1 J2 pin 1 H7 pin 1 H4 pin 1 H3 pin 1 H2 pin 1 J3 pin 1 J5 pin 1 J4 pin 1 H8 pin 1 H0 pin 1 ...

Page 13: ...32 or RS485 driver for 3rd UART on the host controller H7 3x1 Ethernet chip select selector 586 Engine jumper on pins 1 2 H8 2x1 VOFF Jumpers VOFF to Ground 3 4 2 Expansion Headers J1 and J2 J2 Signal GND 40 39 VCC 38 37 ET 36 35 TXD0 34 33 INT RXD0 32 31 RTS1 30 29 TXD1 28 27 RXD1 26 25 24 23 P22 CTS1 22 21 P21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 GND 2 1 J1 Signal VCC 1 2 GND MPO 3 4 C...

Page 14: ...nal active high CS6 8 bit chip select on the host WR active low when write operation RD active low when read operation Signal definitions for J2 VCC 5V power supply GND Ground Pxx PIO pins TxD0 transmit data of serial channel 0 RxD0 receive data of serial channel 0 TxD1 transmit data of serial channel 1 RxD1 receive data of serial channel 1 CTS1 Clear to Send signal for SER1 RTS0 Request to Send s...

Page 15: ...ons U13 2982 AD H2 J6 U3 DAC U2 CS89 U1 PPI J5 J4 J3 J1 J2 H3 H4 H1 U6 HP2020 U8 HP2020 U14 2003 HC14 HC14 1019 324 232 232 10BT 324 U5 PAL P2 P1 P6 P3 P4 P5 P7 P8 SER0 SER1 SCC 12V GND 0 0 3 48 0 18 4 27 0 23 4 33 0 68 1 88 0 19 0 13 0 13 4 33 1 28 4 33 2 03 4 43 3 08 4 31 2 73 2 18 2 99 4 23 0 78 3 37 2 49 3 08 2 99 0 11 0 44 0 17 0 59 0 33 2 53 0 13 2 73 ...

Page 16: ... 7 F A 4 6 V A 4 5 R B 4 4 R B 4 3 F B 4 2 V B 4 1 R C 4 0 R C 3 9 F C 3 8 V C 3 7 RD 36 RD 35 FD 34 VD 33 V 32 G 31 PD 30 RST 29 G 28 LD 27 R W 26 CS 25 D 7 1 3 D 6 1 4 D 5 1 5 D 4 1 6 D 3 1 7 D 2 1 8 D 1 1 9 D 0 2 0 I V D 2 1 G 2 2 A 1 2 3 A 0 2 4 U3 DA8544 V33 CV LD GND RST VCC GND GND DA4 VCC RF5 GND GND GND GND GND AD15 VCC D1 D0 A2 AG 1 AV 2 A0 3 BYTE 4 A B 5 DG 6 IMPUL 7 S P 8 D0 9 D1 10 D2...

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