Teridian 71M6513, User Manual

Page: 44 / 113

71M6513/71M6513H Demo Board User’s Manual
Page: 44 of 112
©
2005-2006 TERIDIAN Semiconductor Corporation
Revision 5.6
From the voltage measurement, we determine that
1.
Î
1
+ =
V XV
E A
We use the other two measurements to determine
φ
S
and A
XI
.
2.
1 ) cos( 1
) 0 cos(
) 0 cos(
0
− = −
−
=
S XI XV
S XI XV
A A
IV
A A IV
E
φ
φ
2a.
) cos(
1
0
S
XI XV
E
A A
φ
+
=
3.
1
) 60 cos(
) 60 cos(
1
) 60 cos(
) 60 cos(
60
−
−
= −
−
=
S
XI XV
S XI XV
A A
IV
A A IV
E
φ φ
3a.
[ ]
1
) 60 cos(
) sin( ) 60 sin( ) cos( ) 60 cos(
60
−
+
=
S S XI XV
A A
E
φ φ
1 ) sin( ) 60 tan( ) cos(
− + =
S XI XV S XI XV
A A A A
φ φ
Combining 2a and 3a:
4.
) tan( ) 60 tan( ) 1 (
0 0 60 S
E E E
φ
+ + =
5.
) 60 tan( ) 1 (
) tan(
0
0 60
+
−
=
E
E E
S
φ
6.
Î




+
−
=
−
) 60 tan( ) 1 (
tan
0
0 60
1
E
E E
S
φ
and from 2a:
7.
Î
) cos(
1
0
S XV
XI
A
E
A
φ
+
=
Now that we know the A
XV
, A
XI
, and
φ
S
errors, we calculate the new calibration voltage gain coefficient from the
previous ones:
XV
NEW
A
V CAL
V CAL
_
_
=
We calculate PHADJ from
φ
S
, the desired phase lag:
[ ]
[ ]






− − − −
− − − +
=
− −
− −
) 2 cos( ) 2 1 ( 1 ) tan( ) 2 sin( ) 2 1 (
) 2 cos( ) 2 1 ( 2 ) 2 1 ( 1 ) tan(
2
0
9
0
9
0
9 2 9
20
T f T f
T f
PHADJ
S
S
π φ π
π φ
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