Demonstration
21
Set the rotary switch (SW2) to the 0 position
Power on the Stratix IV GX FPGA Development Board and download the SOF file
(hsmc_loopback.sof)
Press the CPU reset button located on the host board to initiate the test
Press and release PB0, enabling comma detect
Press and release PB1 enabling channel bonding
Press and release PB2, start transmitting PRBS data
LED0, LED1, and LED2 should be ON and LED3 should be OFF.
Remove one of the SFP modules or one side of a connector so that the loopback will fail. A Failure
is indicated on the Stratix IV GX FPGA Dev Kit when LED3 turns ON
To reset the board test system, press and release the CPU reset button on the host board
Press and release PB1 and PB2 at the same time creates an error in the transmitter data stream,
where LED3 should be ON
Press and release, the CPU reset button on the host board and verify the results
4.5
4.5 Overview
This section describes the design concepts for the SFP HSMC demonstration.
The demonstration is operating on Stratix GX Development Board HSMC Port B interface testing the four
Transceiver/LVDS channels at 6.25Gbps. The transceiver signals HSMB[0:3] on the Stratix IV GX FPGA
Development board are looped back through the SFP HSMC daughter board. The SFP HSMC board must
have SFP modules inserted in SFP[0:3] locations with a loopback from SFP TX to SFP RX on each module.
Four transceiver channels of pseudo-random data are 8B/10B encoded, serialized, pre-emphasized and
transmitted out according to the following signals HSMB_TX_P/N[3:0] of the Stratix IV GX device at
6.25Gbps. These high-speed serial data are then looped back through an external SFP HSMC back to the
Stratix IV GX device. Through the SFP HSMC board the data is then equalized, retimed, deserialized, word
aligned, 8B/10B decoded, channel bonded, and then the four bonded channels are compared against a
receive side PRBS generator inside the Stratix IV GX FPGA fabric.
The demonstration function block diagram is shown below in figure 4.5
