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Board Components

17

3.3

3.3 Power Supply

This section describes the power supply on the SFI HSMC board

The SFP HSMC is powered through the HSMC connector’s 3.3V and 12V pins. The SFP and clocking

circuitry requires 3.3V. A switching regulator powered from the 12 HSMC input produces 4V. Three linear

regulators powered from 4V will produce the 3.3V. The switching frequency is set to 1MHz. The power

distribution network is shown in the figure below. Max power consumption is estimated at 1A on 12V.

Typical power consumption is considerably less than this.

Figure 3.3 Power distribution on the SFP HSMC board

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Summary of Contents for SFP HSMC

Page 1: ...Terasic THDB SUM SFP HSMC Terasic SFP HSMC Board User Manual Document Version 1 00 AUG 12 2009 by Terasic ...

Page 2: ...NETS 6 2 2 2 2 BLOCK DIAGRAM 8 BOARD COMPONENTS 9 3 1 3 1 THE SFP HSMC CONNECTOR 9 3 2 3 2 CLOCK CIRCUITRY 15 3 3 3 3 POWER SUPPLY 17 DEMONSTRATION 18 4 1 4 1 INTRODUCTION 18 4 2 4 2 SYSTEM REQUIREMENTS 18 4 3 4 3 SETUP THE DEMONSTRATION 18 4 4 4 4 DEMO OPERATION 20 4 5 4 5 OVERVIEW 21 APPENDIX 23 5 1 5 1 REVISION HISTORY 23 5 2 5 2 ALWAYS VISIT SFP HSMC WEBPAGE FOR NEW MAIN BOARD 23 ...

Page 3: ...for customers to implement both telecommunication and data communications applications 1 11 1 Features Figure 1 1 shows the photo of the SFP HSMC board The important features are listed below 8 SFP Connectors 4 Transceiver Based SFPs 4 LVDS Bases SFPs 8 SMAs 2 Transceiver Receive SMAs 2 Transceiver Transmit SMAs 1 LVDS Clock Input SMA pair 2 SMAs 2 Single ended Clock Outputs SMAs 1 LVDS Clock Outp...

Page 4: ...MC Board 1 21 2 About the KIT This section describes the package content SFP HSMC Board x 1 System CD ROM x 1 The CD contains technical documents of the SFP HSMC and reference designs along with the source code Figure 1 2 SFP HSMC Package ...

Page 5: ...Introduction 3 1 31 3 Assemble the SFP HSMC Board This section describes how to connect the SFP HSMC board to a main board The SFP HSMC board connects with Altera DE3 Board ...

Page 6: ...ix IV GX FPGA Development Board The SFP HSMC board connects with Altera Stratix III FPGA Deveopment Kit Note Do not attempt to connect remove the SFP HSMC daughter board to from the main board when the power is on or else the hardware could be damaged ...

Page 7: ...Introduction 5 1 41 4 Getting Help Here are some places to get help if you encounter any problem Email to support terasic com Taiwan China 886 3 550 8800 Korea 82 2 512 7661 Japan 81 428 77 7000 ...

Page 8: ...rd including its PCB and block diagram 2 1 2 1 Layout and Componets The picture of the SFP HSMC board is shown in Figure 2 1 and Figure 2 2 It depicts the layout of the board and indicates the location of the connectors and key components Figure 2 1 The SFP HSMC PCB and component diagram ...

Page 9: ...CVR SFP Dip Switch S5 XCVR LVDS Dip Switch S4 CLK2_SMA_p J14 CLK2_SMA_n J15 SMA_CLK1 J9 PLL 4 1 Input Multiplexer Dip Switch S3 PLL 4 1 Input Multiplexer Dip Switch S2 SMA_REFCLK J11 SMA_REFCLK_n J8 SMA_REFCLK_p J4 CLOCK Dip Switch S1 XCVR_TX4n J5 XCVR_TX4p J1 XCVR_TX4n J6 XCVR_RX4p J2 SMA_CLK_n J7 SMA_CLK_p J3 HSMC Connector J17 XCVR SFP 0 3 J16 ...

Page 10: ...Architecture 8 2 2 2 2 Block Diagram Figure 2 3 shows the block diagram of the SFP HSMC board Figure 2 3 The block diagram of the SFP HSMC board ...

Page 11: ...ables of the SFP HSMC board 3 1 3 1 The SFP HSMC Connector This section describes pin definition of the SFP HSMC interface onboard All the control and data signals of the SFPs are connected to the HSMC connector so users can fully control the SFP HSMC daughter board through the HSMC interface Power is derived from 3 3V and 12V of the HSMC connector ...

Page 12: ...Board Components 10 Figure 3 1 The pin outs on the HSMC connector ...

Page 13: ...Dp Input Receiver Non Inverted Data Output 19 SFP3_TDn Output Transmitter Inverted Data Input 20 SFP3_RDn Input Receiver Inverted Data Output 21 SFP2_TDp Output Transmitter Non Inverted Data Input 22 SFP2_RDp Input Receiver Non Inverted Data Output 23 SFP2_TDn Output Transmitter Inverted Data Input 24 SFP2_RDn Input Receiver Inverted Data Output 25 SFP1_TDp Output Transmitter Non Inverted Data Inp...

Page 14: ...nt 54 SFP3_RATESEL Output Rate Select 55 SFP3_LOS Input Receiver Loss of Signal Indication 56 SFP2_TXFAULT Input Module Transmitter Fault 57 3V3 Power Power 3 3V 58 12V Power Power 12V 59 SFP2_TXDISABLE Output Transmitter Disable Turns off transmitter laser output 60 SFP2_MOD2_SDA Inout SDA Serial Data Signal 61 SFP2_MOD1_SCL Output SCL Serial Clock Signal 62 SFP2_MOD0_PRSNTn Input LED indicator t...

Page 15: ...d Data Output 91 SFP4_TDn Output Transmitter Inverted Data Input 92 SFP4_RDn Input Receiver Inverted Data Output 93 3V3 Power Power 3 3V 94 12V Power Power 12V 95 SFP4_TXFAULT Input Module Transmitter Fault 96 CLK1_p Input Differential Clock Input 97 SFP4_TXDISABLE Output Transmitter Disable Turns off transmitter laser output 98 CLK1_n Input Differential Clock Input 99 3V3 Power Power 3 3V 100 12V...

Page 16: ...Data Output 129 3V3 Power Power 3 3V 130 12V Power Power 12V 131 SFP6_TXFAULT Input Module Transmitter Fault 132 SFP6_TXDISABLE Output Transmitter Disable Turns off transmitter laser output 133 SFP6_MOD2_SDA Inout SDA Serial Data Signal 134 SFP6_MOD1_SCL Output SCL Serial Clock Signal 135 3V3 Power Power 3 3V 136 12V Power Power 12V 137 SFP6_MOD0_PRSNTn Input LED indicator that the module is prese...

Page 17: ...160 GND Power Power Ground 3 2 3 2 Clock Circuitry This section describes the board s clock inputs and outputs LVDS clock frequencies of 61 44MHz 125MHz 155 52MHz or 156 25MHz can be selected for HSMC CLK1p CLK1n CLK1p CLk1n will be converted to a single ended clock signal and output to an SMA LVDS clock frequencies of 125MHz 155 52MHz 156 25MHz or SMA_CLKp n can be selected for HSMC CLK2p CLK2n p...

Page 18: ...agram Table 3 2 CLK1 Settings SEL 1 0 CLK1p CLK1n Frequency 11 125 00 MHz Default 10 155 52 MHz 01 156 25 MHz 00 61 44 MHz Table 3 3 CLK2 Settings SEL 3 2 CLK2p CLK2n Frequency 11 125 00 MHz Default 10 155 52 MHz 01 156 25 MHz 00 SMA_CLK_p n ...

Page 19: ...itry requires 3 3V A switching regulator powered from the 12 HSMC input produces 4V Three linear regulators powered from 4V will produce the 3 3V The switching frequency is set to 1MHz The power distribution network is shown in the figure below Max power consumption is estimated at 1A on 12V Typical power consumption is considerably less than this Figure 3 3 Power distribution on the SFP HSMC boar...

Page 20: ...ghter board and the Stratix IV GX FPGA Development board The demonstration is intended for users to provide a basic introduction to the SFP HSMC daughter board with the procedure to control different hardware and software settings 4 2 4 2 System Requirements The following items are required for the HSMC DVI Server demonstration SFP HSMC x 1 Stratix IV GX FPGA Development Board x 1 SFP Loopback Con...

Page 21: ...tion 19 Figure 4 3 Transceiver Loopback Test Setup Figure 4 4 LVDS Loopback Test Setup Note The SFP HSMC board must be connected to HSMC Slot B of the Stratix IV GX FPGA Development Board for this demonstration ...

Page 22: ...e PB0 enabling comma detect Press and release PB1 enabling channel bonding Press and release PB2 start transmitting PRBS data LED0 LED1 and LED2 should be ON and LED3 should be OFF Remove one of the SFP modules or one side of a connector so that the loopback will fail A Failure is indicated on the Stratix IV GX FPGA Dev Kit when LED3 turns ON To reset the board test system press and release the CP...

Page 23: ...w This section describes the design concepts for the SFP HSMC demonstration The demonstration is operating on Stratix GX Development Board HSMC Port B interface testing the four Transceiver LVDS channels at 6 25Gbps The transceiver signals HSMB 0 3 on the Stratix IV GX FPGA Development board are looped back through the SFP HSMC daughter board The SFP HSMC board must have SFP modules inserted in SF...

Page 24: ...tect PB1 Enable Channel Bond PB2 Start Transmitting PRBS data PB1 PB2 Pressing PB1 and PB2 at the same time creates and error in the transmitter data stream USER_LED 0 PLLs are locked USER_LED 1 Pattern Sync Acquired Word aligned Channel Bonded 1st PRBS Data Received USER_LED 2 Test Complete USER_LED 3 Error USER_LED 15 4 Heartbeat Pattern Board is active ...

Page 25: ...2009 Initial Version April 20 2013 Modify some board name 5 2 5 2 Always Visit SFP HSMC Webpage for New Main board We will be continuing providing interesting examples and labs on our SFP HSMC webpage Please visit www altera com or hsmcsfp terasic com for more information ...

Page 26: ...Mouser Electronics Authorized Distributor Click to View Pricing Inventory Delivery Lifecycle Information Terasic P0040 ...

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