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SDI-FMC User Manual

20

www.terasic.com

April 22, 2019

detected
L: HD/3G/6G/12G data
rate detected

FMC_SDI_12G_RC_LOS0

C14

SDI 12G TX 0
Reclocker LOS signal,

Signal

Detect

Complement

H:  No  input  signal  is
present  or  the  cable
length  is  above  the
MUTEREF threshold

L: Input signal is
present and cable length
is below the
MUTEREF threshold

Input

VCCADJ

FMC_SDI_12G_RC_ALARM_n0 C11

SDI 12G TX 0
Reclocker ALARM
signal,

Active low (open drain)

H: Normal operation

L: Alarm asserted

Input

VCCADJ

FMC_SDI_12G_RC_LOS1

C12

SDI 12G TX 1
Reclocker LOS signal,

Signal

Detect

Complement

H:  No  input  signal  is
present  or  the  cable
length  is  above  the
MUTEREF threshold

L: Input signal is

Input

VCCADJ

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Summary of Contents for SDI-FMC

Page 1: ......

Page 2: ...board 4 1 3 Connectivity 6 1 4 Getting Help 7 Chapter 2 Architecture of SDI FMC 8 2 1 Features 8 2 2 Layout and Block Diagram 8 Chapter 3 Using the SDI FMC 13 3 1 Pin Definition of FMC Connector 13 3...

Page 3: ...Block Diagram 33 4 3 Demo on A10SoC FPGA Mainboard 35 4 4 Demo on A10GFP FPGA Mainboard 39 4 5 Demo on HAN Pilot Platform 43 4 6 Si5344 Configuration IP 48 4 7 LMH1983 Configuration IP 49 Chapter 5 A...

Page 4: ...ria 10 GX FPGA Development Kit A10GFP and Arria 10 SoC Development Kit A10SoC 1 1 1 1 T Th he e P Pa ac ck ka ag ge e C Co on nt te en nt ts s The SDI FMC kit comes with the following items SDI FMC Da...

Page 5: ...es as shown in Figure 1 2 Users can use the screws copper pillars and nuts that come with the SDI FMC to secure the SDI FMC on the FPGA mainboard as shown in Figure 1 3 In order to use the 12G SDI hig...

Page 6: ...for installation of the brackets for the SDI FMC Note The height of these brackets is designed specifically for the Intel A10SoC and A10GFP These brackets may not be suitable for other FPGA mainboards...

Page 7: ...vi it ty y Figure 1 6 and Figure 1 7 below show the connectivity of the SDI FMC to the A10SoC and A10GFP FPGA boards The SDI FMC is powered from FPGA mainboard It is not necessary to connect a power...

Page 8: ...erasic com April 22 2019 1 1 4 4 G Ge et tt ti in ng g H He el lp p For Technical Support Terasic s Contact Information is listed below Office Hours 9 00 a m to 6 00 p m GMT 8 Telephone 886 3 575 0880...

Page 9: ...module are listed below Two 12G SDI inputs and outputs Connected to 4 75 Ohm BNC connector Two 3G SDI inputs or outputs Connected to 2 75 Ohm BNC connector Two AES inputs and outputs Connected to 2 75...

Page 10: ...2 2019 Figure 2 1 Top view of the SDI FMC Daughter Card The bottom view of the SDI FMC is shown in Figure 2 2 It depicts the layout and indicates the locations of connectors and key components Figure...

Page 11: ...g port connected to the BNC connectors The six 12G SDI chips can be configured through the SPI chain There are also two independent 3G SDI channels in the boards Each channel can be configured as eith...

Page 12: ...red clock sources for SDI application Please note when users connect the SDI FMC card to FPGA main board and power on it the FPGA should reset the clock generator Si5344 first to output the correct fr...

Page 13: ...SDI FMC User Manual 12 www terasic com April 22 2019 Figure 2 5 Clock Functions in the Block diagram...

Page 14: ...d how to use the 12G SDI 3G SDI AES and clock generator hardware in the board 3 3 1 1 P Pi in n D De ef fi in ni it ti io on n o of f F FM MC C C Co on nn ne ec ct to or r The FMC connector on the SDI...

Page 15: ...SDI FMC User Manual 14 www terasic com April 22 2019 Figure 3 2 Signal names of FMC connector part 2 Figure 3 3 Signal names of FMC connector part 3...

Page 16: ...signal Output VCCADJ VCG_F H11 LMH1983 Field sync odd even reference signal Output VCCADJ VCG_INIT C10 LMH1983 Reset signal for audio video phase alignment rising edge triggered Output VCCADJ VCG_NO_L...

Page 17: ...H26 Select Reference Clock 0 input source bit 1 Output VCCADJ FMC_CLKSEL_S20 D23 Select Reference Clock 1 input source bit 0 Output VCCADJ FMC_CLKSEL_S21 D24 Select Reference Clock 1 input source bit...

Page 18: ...vice Output Enable Disables all outputs when held high Output VCCADJ FMC_SI5344_IN_SEL0 G37 Input Reference Select bit0 Output VCCADJ FMC_SI5344_IN_SEL1 D17 Input Reference Select bit1 Output VCCADJ F...

Page 19: ...t VCCADJ FMC_SDI_12G_SPI_SDI H23 SDI 12G SPI interface Slave data input signal Output VCCADJ FMC_SDI_12G_SPI_SDO H22 SDI 12G SPI interface Slave data output signal Input VCCADJ FMC_SDI_12G_RX_LOS0 C15...

Page 20: ...DI_12G_RX_LOS1 C18 SDI 12G RX 1 LOS signal Signal Detect Complement H No input signal is present or the cable length is above the MUTEREF threshold L Input signal is present and cable length is below...

Page 21: ...the MUTEREF threshold L Input signal is present and cable length is below the MUTEREF threshold Input VCCADJ FMC_SDI_12G_RC_ALARM_n0 C11 SDI 12G TX 0 Reclocker ALARM signal Active low open drain H Nor...

Page 22: ...ce Data Master Input Slave Output Input VCCADJ FMC_SDI_3G_SPI_MOSI H29 SDI 3G SPI Interface Data Master Output Slave Input Output VCCADJ FMC_SDI_3G_SPI_SCK D26 SDI 3G SPI Interface Serial clock Output...

Page 23: ...l 0 Transmitter output driver enable Internal pullup H output driver is enabled L output driver is powered off Output VCCADJ FMC_SDI_3G_TX_EN1 G27 SDI 3G Channel 1 Transmitter output driver enable Int...

Page 24: ...3G HD Output VCCADJ FPGA_CLK_p H13 For Si5344 input reference clock 1 Output VCCADJ FPGA_CLK_n H14 For Si5344 input reference clock 1 Output VCCADJ FMC_AES_IN0 C22 AES Channel 0 input Input VCCADJ FMC...

Page 25: ..._n1 B21 Transceiver Reference clock 0 297 0 1 001MHz input Input VCCADJ SDI_12G_TX_p0 A26 SDI 12G Transmitter Channel 0 Output VCCADJ SDI_12G_TX_n0 A27 SDI 12G Transmitter Channel 0 Output VCCADJ SDI_...

Page 26: ...igure 3 4 shows the system block diagram of the 12G SDI The M23145 Reclocker chips and MACD23528 Cable Driver chips are used to transmit the 12G SDI signal and the M23554 Cable Equalizer chips are use...

Page 27: ...transceiver pins The BNC connecters are used as an interface to connect external 3G SDI signals The LMH0387 chips can be configured either in the input mode as an equalizer to receiver data over coax...

Page 28: ...l delivers a 75 load termination with a return loss of 25 dB or more The signal is inputted through a 75 BNC and terminated with a 75 resistor to ground The unbalanced signal is then balanced through...

Page 29: ...f the RS422 transceiver has an RX network to limit the output slew rate thus limiting the bandwidth of AES3 output The AES3 channel is designed to support 192 kHz to 24 kHz sample rates The output is...

Page 30: ...z as a reference clock for Si5344 chip In the demonstration project Terasic provides the Si5344 and LMH1983 configure IP so developers can easily configure these clock generator chips to generate the...

Page 31: ...SDI FMC User Manual 30 www terasic com April 22 2019 Figure 3 9 Clock Generator System Block Diagram...

Page 32: ...GA Mainboard SDI FMC Daughter Card 12G SDI BNC to BNC Cable x2 3G SDI BNC to BNC Cable x1 4 4 1 1 D De em mo o D De es sc cr ri ip pt ti io on n Figure 4 1 shows the data path of the loopback test for...

Page 33: ...case the first 3G SDI chip is configured as output mode and the second SDI chip is configured as input mode A BNC to BNC cable is used to loopback the SDI signal from one BNC connector to another Figu...

Page 34: ...o configure Si5344 chip through I2C interface to generate the required 297MHz clock The Si5344 required 27MHz reference which can come from either LMH1983 chip on the SDI FMC board or from FPGA mainbo...

Page 35: ...is performed because the 3G SDI chip is a bi direction chip The SWICH0 is used to switch the direction Each pattern generator and checker is created based on Quartus SDI II IP The LED2 and LED3 are u...

Page 36: ...SDI FMC should be installed on the FMC A expansion header of the A10SoC Use one BNC to BNC 3G SDI Cable to connect the BNC port J10 and BNC port J13 Use one BNC to BNC 12G SDI Cable to connect the BN...

Page 37: ...it means the two channel 12G SDI loopback test passed 9 Set the SW2 5 dip switch to down as shown in Figure 4 8 and observe LED2 If the LED is lit it means the 3G SDI Loopback test passed Then set SW...

Page 38: ...hten when 12G Channel 0 receives a valid SDI pattern LED1 D25 Lighten when 12G Channel 1 receives a valid SDI pattern LED2 D28 Case 1 When SWITCH0 SW2 5 is 0 Up Position Lighten when 3G Channel 0 rece...

Page 39: ...Position Lighten when 3G Channel 1 receives a valid SDI pattern BUTTON0 S3 SYSTEM reset BUTTON1 S5 12G cable driver IC mute control Button Pressed MUTE Button Released UNMUTE BUTTON2 S6 Video Standard...

Page 40: ...oC_12G_SDI folder from the SDI FMC System CD 4 4 4 4 D De em mo o o on n A A1 10 0G GF FP P F FP PG GA A M Ma ai in nb bo oa ar rd d This section shows how to setup the demo on the A10GFP Arria 10 FPG...

Page 41: ...Mini USB cable 5 Power on the FPGAA10GFP board 6 Make sure the Quartus Prime and the USB Blaster II driver have been installed on the host PC 7 Copy the folder Demonstrations A10GFP_12G_SDI demo_batch...

Page 42: ...Make sure R1086 is installed default for 1 8V Figure 4 11 BUTTON SWITCH LED on A10GFP Table 4 2 Functional keys of the A10GFP 12G 3G SDI RX TX demonstration Name Description LED0 D10 Lighten when 12G...

Page 43: ...LED3 D7 Case 1 When SWITCH0 SW2 5 is 0 Down Position Lighten when LMH1983 detects an expected video signal coming from the J7 Video in BCN connector Case 2 When SWITCH0 SW2 5 is 1 Up Position Lighten...

Page 44: ...e of Quartus project for the loopback demo with the A10GFP board is available in the Demonstrations A10GFP_12G_SDI folder from the SDI FMC System CD 4 4 5 5 D De em mo o o on n H HA AN N P Pi il lo ot...

Page 45: ...platform Use an BNC to BNC 3G SDI Cable to connect BNC port J10 and the BNC port J13 Use an BNC to BNC 12G SDI Cable to connect the BNC port J11 and BNC port 15 and use another BNC to BNC 12G SDI Cabl...

Page 46: ...D1 as shown in Figure 4 14 If two LEDs light up it means the two channels 12G SDI loopback test are pass 9 Set the SW0 switch to Down as shown in Figure 4 14 and observe HEX0_DP dot point If the dot p...

Page 47: ...en set SW0 to logic 0 Down Position Lights up when 3G Channel 0 receives a valid SDI pattern Case 2 When set SW0 to logic 1 Up Position Lights up when LMH1983 detects an expected video signal coming f...

Page 48: ...For 12G SDI Loopback Test Button Pressed SD SDI Button Released 12G SDI For 3G SDI Loopback Test Button Pressed SD SDI Button Released 3G SDI SW0 3G SDI Loopback direction control 1 Up CH0 TX CH1 RX 0...

Page 49: ...IP can be used to configure Si5344 to generate the following clock setting OUT0 297 0 MHz clock which is connected to GBTCLK_M2C_P0 OUT1 22 5792 MHz clock which is connect co MUX DS250 OUT2 254 MHz c...

Page 50: ...74 176 MHz clock which is connected to MUX DS250 OUT3 24 579 or 98 304 MHz clock which is connect to MUX DS250 The OUT0 clock can be used as a reference clock for the Si5344 clock generator The LMH198...

Page 51: ...erasic com April 22 2019 Figure 4 16 MODE1 Video Timing Generation for HD SDI Up Conversion Figure 4 17 MODE2 A V Clock Generation with Recognized Clock Base Input Reference Figure 4 18 MODE3 A V Cloc...

Page 52: ...SDI FMC User Manual 51 www terasic com April 22 2019 The IP named as LMH1983_CONFIG is defined below In this demonstration MODE0 and MODE3 are used...

Page 53: ...V1 1 10 26 2018 Add Note for section 2 2 and 3 5 modify Figure 2 5 and Figure 3 9 V1 2 04 11 2019 Add section 4 5 12G SDI demo for HAN Pilot Platform 5 5 2 2 C Co op py yr ri ig gh ht t S St ta at te...

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