Terasic MTLC, User Manual, Page: 36 / 39

MTLC User Manual
34
www.terasic.com
May 22, 2014

Batch File: VIP_Camera.bat, VIP_Camera _bashrc

FPGA Configuration File: VIP_Camera.sof

Nios II Program: VIP_Camera.elf

Demonstration Setup

Connect the VGA output of the VEEK-MT to a VGA monitor (both LCD and CRT type of
monitors should work)

Load the bit stream into FPGA (note*)

Run the Nios II and choose VIP_Camera\Software as the workspace. Click on the Run button
(note *)

The system enters the FREE RUN mode automatically. Press KEY[0] on the DE2-115 board to
reset the circuit

Press KEY[2] to stop run; you can press KEY[3] again to switch back to FREE RUN mode
and you should be able to see whatever the camera captures on the VGA display

User can use SW[17] to mirror image of the line. However, remember to press KEY[0] after
toggle SW[17]

Press and drag the video frame box will result in scaling the playing window to any size, as
shown in
Figure 4-14
Note:
(1).Execute VIP_Camera\demo_batch\VIP_CameraA.bat will download .sof and .elf files.
(2).You may need additional Altera VIP suite Megacore license features to recompile the project.
Figure 4-14 illustrates the setup for this demonstration.
Figure 4-14 Setup for the VIP_Camera demonstration