Terasic HAN Pilot Platform, Demonstration Manual, Page: 110 / 117

HAN Pilot Platform
Demonstration Manual 109 www.terasic.com
September 6, 2019
14. Type 5 followed by an ENTER key to select DMA DDR4-B Memory Test item. The DMA write
and read test result will be report as shown in
Figure 6-18 .
Figure 6-18 Screenshot of DDR4-B SODIMM Memory DAM Test Result
15. Type 99 followed by an ENTER key to exit this test program.

Development Tools

Quartus Prime 18.0 Standard Edition

GNU Compiler Collection, Version 4.8 is recommended

Demonstration Source Code Location

Quartus Project: Demonstrations\PCIE_DDR4

Visual C++ Project: Demonstrations\PCIe_SW_KIT\Windows\PCIe_DDR4

FPGA Application Design
Figure 6-19 shows the system block diagram in the FPGA system. In the Qsys, Altera PIO
controller is used to control the LED and monitor the Button Status, and the On-Chip memory is
used for performing DMA testing. The PIO controllers and the On-Chip memory are connected to
the PCI Express Hard IP controller through the Memory-Mapped Interface.