Terasic Apollo Carrier Board, User Manual

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Apollo Carrier Board
User Manual 11 www.terasic.com
September 22, 2020
FMC_GPIO_D[30] GPIO Connection[30] 3.3(Default)/2.5/1.8V G24 PIN_A17
FMC_GPIO_D[31] GPIO Connection[31] 3.3(Default)/2.5/1.8V H26 PIN_A21
FMC_GPIO_D[32] GPIO Connection[32] 3.3(Default)/2.5/1.8V H23 PIN_B22
FMC_GPIO_D[33] GPIO Connection[33] 3.3(Default)/2.5/1.8V H25 PIN_A20
FMC_GPIO_D[34] GPIO Connection[34] 3.3(Default)/2.5/1.8V G16 PIN_B20
FMC_GPIO_D[35] GPIO Connection[35] 3.3(Default)/2.5/1.8V G25 PIN_B17
2.4 Clock Generator
The Carrier board includes one Si5340A clock generator to provide reference clock for FPGA
transceiver IP as shown in Figure 2-8 . To enable the clock generator, developers must well control
the control pins Si5340A_OE_n and Si5340A_RST_n on the Si5340A.
Figure 2-8 Si5340A of the Carrier Board
Table 2-5 Clock Generator Pin Assignments, Schematic Signal Names, and Functions
Schematic
Signal Name
Description I/O Standard Default Freq.
FMC+
Pin Num.
Apollo S10
FPGA Pin Num.
FMCP_REFCLK_p
Reference clock FMC+
connector
LVDS 644.53125MHz D4 PIN_AM41
QSFP28A_REFCLK_p
Reference clock for
QSFP28A
LVDS 644.53125MHz L8 PIN_AM38
QSFP28B_REFCLK_p
Reference clock for
QSFP28B
LVDS 644.53125MHz L4 PIN_T41
Si5340A_I2C_SCL
I2C clock bus of the
clock generator
1.8V -- H32 PIN_AU34
Si5340A_I2C_SDA
I2C data bus of the
clock generator
1.8V
-- G34 PIN_AU33
SI5340A_OE_n
Enable output of the
clock generator
1.8V
-- G31 PIN_BG38
SI5340A_RST_n Reset of the clock 1.8V -- H31 PIN_BG37