Apollo Carrier Board
User Manual
39
www.terasic.com
September 22, 2020
PCIE_HANDLE hPCIE,
uint32_t Offset,
uint32_t *pdwData
);
Parameters:
hPCIE:
A PCIe handle return by PCIE_Open function.
Offset:
Specify the target byte of offset in PCIe configuration table.
pdwData:
A 4-bytes buffer to retrieve the 32-bit data.
Return Value:
Return
true
if read data is successful; otherwise
false
is returned.
5.5
PCIe Reference Design - DDR4
The application reference design shows how to add the DDR4 Memory Controllers for the on board
DDR4A and DDR4B banks into the PCIe Quartus project and perform 16GB data DMA for both
SODIMM. Also, this demo shows how to call “PCIE_ConfigRead32” API to check PCIe link status.
Demonstration Files Location
The demo file is located in the batch folder:
CDROM\Demonstrations\PCIe_DDR4\demo_batch
The folder includes following files:
FPGA Configuration File: S10C_top.sof
Download Batch file: test.bat
Windows Application Software folder: windows_app, includes
PCIE_DDR4.exe
TERASIC_PCIE_AVMM.dll
Demonstration Setup
1. Connect the Apollo develop kit and the Host PC with Thunderbolt 3 cable.
2. Make sure the Intel Quartus Programmer and USB-Blaster II driver are installed.
3. Execute test.bat in "CDROM\Demonstrations\PCIe_DDR4\demo_batch" to configure the FPGA
4. Install the PCIe driver if necessary. The driver is located in the folder:
CDROM\Demonstration\PCIe_SW_KIT\Windows\PCIe_Driver.
5. Pull the Thunderbolt 3 cable off form the Host, then pull the cable in again for redetect the PCIe
device
6. Make sure that Windows has detected the FPGA Board by checking the Windows Device
