TR5-F40W
User
Manual
18
June 20, 2018
TEMPDIODEn
Negative pin of temperature diode in
Stratix V
2.5-V
PIN_P5
TEMP_CLK
SMBus clock
2.5-V
PIN_AM17
TEMP_DATAT
SMBus data
2.5-V
PIN_AN17
TEMP_OVERT_n
SMBus alert (interrupt)
2.5-V
PIN_AR17
TEMP_INT_n
SMBus alert (interrupt)
2.5-V
PIN_AT17
FAN_CTRL
Fan control
2.5-V
PIN_AW16
2
2
.
.
5
5
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The development board includes one 50 MHz and two programmable oscillators
.
shows
the default frequencies of on-board all external clocks going to the Stratix V GX FPGA. The figures
also show an off-board external clock from PCI Express Host to the FPGA. Lastly, there is an SMA
connector for clock input, and an SMA connector for clock output.
Figure 2-9
Clock Circuit of the FPGA Board
A clock buffer is used to duplicate the 50 MHz oscillator, so each bank of FPGA I/O bank 3/4/7/8
has two clock inputs. The two programming oscillators are low-jitter oscillators which are used to
provide special and high quality clock signals for high-speed transceivers.
