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TENX TECHNOLOGY TM57PE10, User Manual

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Advance Information 
 

UM-TM57PE10_E 

 8-Bit Microcontroller  

 

10

                           tenx technology inc.  

Preliminary

                                                                                   

Rev 1.4,  2012/01/19 

 

 

FUNCTIONAL DESCRIPTION  

1. CPU Core 

1.1   Clock Scheme and Instruction Cycle 

The system clock is internally divided by two to generate Q1 state and Q2 state for each instruction 
cycle. The Programming Counter (PC) is updated at Q1 and the instruction is fetched from program 
ROM and latched into the instruction register in Q2. It is then decoded and executed during the following 
Q1-Q2 cycle. Branch instructions take two cycles since the fetch instruction is ‘flushed’ from the pipeline, 
while the new instruction is being fetched and then executed. 

Fetch

Execute

Branch

Instruction

Instruction

Pipeline

Flow

Fetch

Execute

Fetch

Flush

Fetch

Execute

Instruction

Cycle

F

OSC

Q1

Q2

Q1

Q2

Q1

Q2

Q1

Q2

Q1

Q2

Q1

Q2

 

 

1.2   Addressing Mode 

There are two Data Memory Planes in CPU, R-Plane and F-Plane. The registers in R-Plane are write-
only. The “MOVWR” instruction copy the W-register’s content to R-Plane registers by direct addressing 
mode. The lower  locations of F-Plane  are reserved for the SFR.  Above the SFR is  General Purpose 
Data Memory, implemented as  static RAM.  F-Plane can be addressed directly or indirectly. Indirect 
Addressing is made by INDF register. The INDF register is not a physical register. Addressing INDF 
actually addresses the register whose address is contained in the FSR register (FSR is a pointer). The 
first half of F-Plane is bit-addressable, while the second half of F-Plane is not bit-addressable. 

 

R-Plane 

 

F-Plane 

00 

 

00 

 

 

 

 

SFR 

 

 

 

Bit Addressable 

 

MOVWR Instruction 

 

 

 

Write Only 

1F 

 

 

 

20 

 

 

 

 

SRAM 

 

 

 

Bit Addressable 

 

 

 

 

3F 

 

3F 

 

 

 

40 

 

 

 

 

 

 

 

 

SRAM 

 

 

 

 

 

 

4F 

 

Summary of Contents for TM57PE10

Page 1: ...icense under its patent rights nor the rights of others tenx products are not designed intended or authorized for use in life support appliances devices or systems If Buyer purchases or uses tenx products for any such unintended or unauthorized application Buyer shall indemnify and hold tenx and its officers employees subsidiaries affiliates and distributors harmless against all claims cost damage...

Page 2: ... 2 Add Internal RC mode description and figure in System Clock Oscillator section V1 2 Aug 2011 Modify the operating voltage V1 3 Dec 2011 1 Add Ordering Information table in the Packaging Information section 2 Add 16 pin DIP SOP in Features section 3 Add 16 pin Package Dimension V1 4 Jan 2012 1 Add the Electrical Characteristics specs in the Features section 2 Add description in Reset section 4 M...

Page 3: ...1 6 Interrupt 13 2 Chip Operation Mode 14 2 1 Reset 14 2 2 System Configuration Register SYSCFG 15 2 3 PROM Re use ROM 16 2 4 Power Down Mode 16 2 5 Dual System Clock 17 2 6 Dual System Clock Modes Transition 18 3 Peripheral Functional Block 20 3 1 Watchdog WDT Wakeup WKT Timer 20 3 2 Timer0 8 bit Timer Counter with Pre scale PSC 21 3 3 Timer2 15 bit Timer 22 3 4 PWM0 8 bit PWM 22 3 5 PWM1 8 bit P...

Page 4: ...ute Maximum Ratings 45 2 DC Characteristics 46 3 Clock Timing 48 4 Reset Timing Characteristics 48 6 Characteristic Graphs 48 PACKAGING INFORMATION 51 14 DIP Package Dimension 52 14 SOP Package Dimension 52 16 DIP Package Dimension 53 16 SOP Package Dimension 54 18 DIP Package Dimension 55 18 SOP Package Dimension 55 ...

Page 5: ...mple fixed frequency and duty cycle variable PWM generator 8 One analog voltage comparator 9 Min Operating Voltage power on and Speed VDD 1 5V 4 MHz 10 PA1 PA6 PB1 PB6 individual pin low level wake up 11 Oscillation Sources Fast Clock FXT Fast Crystal 1 MHz 24 MHz FIRC Fast Internal RC 4 8 MHz XRC External R External C 10 KHz 3 MHz Slow Clock SXT Slow Crystal 32768 Hz XRC External R External C 10 ...

Page 6: ... 17 Interrupt Three External Interrupt pins Two pins are falling edge triggered One pin is rising or falling edge triggered Timer0 Timer2 Wake up Timer Interrupt PWM0 CMP interrupt 18 Watchdog Timer Clocked by built in RC oscillator with 4 adjustable Reset Interrupt Time 108 ms 56 ms 28 ms 14 ms 5V 138 ms 72 ms 36 ms 18 ms 3V Watchdog timer can be disabled enabled in STOP mode 19 I O Ports CMOS Ou...

Page 7: ...ecoder W ALU Program Counter STATUS F Plane Register File 5 LEVEL STACK FXT SXT OSC FIRC CLOCK GEN TIMING CTRL RESET T0I PA2 WDT Timeout XRC MUX 8 R Plane Register File MUX 7 FSR 8 Data Bus F plane Indirect Address TIMER0 TIMER0 PRESCALER TIMER2 CPUCLK 128 Slow Clock WDT WKT PB0 PB1 PB2 PB3 PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 8 bit PWM0 PB4 PB5 PB6 PB7 8 bit PWM1 Analog CMP ...

Page 8: ... 5 10 PB5 PWM1 IN0 PB1 6 9 PB4 CMPO IN1 PB2 7 8 PB3 IN PWM0 PA1 1 U 16 PA0 INT0 T0I PA2 2 15 PA4 Xin Xrc VPP nReset INT2 PA7 3 14 PA3 Xout CLKO VSS 4 13 VDD INT1 PB0 5 TM57PE10 12 PB7 IN0 PB1 6 11 PB6 IN1 PB2 7 10 PB5 PWM1 IN PB3 8 9 PB4 CMPO PA5 1 U 18 PA6 PWM0 PA1 2 17 PA0 INT0 T0I PA2 3 16 PA4 Xin Xrc VPP nReset INT2 PA7 4 15 PA3 Xout CLKO VSS 5 TM57PE10 14 VDD INT1 PB0 6 13 PB7 IN0 PB1 7 12 PB...

Page 9: ... by software PA7 I Schmitt trigger input PB0 PB7 I O Bit programmable I O port for Schmitt trigger input CMOS push pull output or open drain output Pull up resistors are assignable by software nRESET I External active low reset Xin Xout Crystal Resonator oscillator connection for system clock Xrc External RC oscillator connection for system clock CLKO O CPU Instruction clock output for external in...

Page 10: ...Fetch Execute Fetch Flush Fetch Execute Instruction Cycle FOSC Q1 Q2 Q1 Q2 Q1 Q2 Q1 Q2 Q1 Q2 Q1 Q2 1 2 Addressing Mode There are two Data Memory Planes in CPU R Plane and F Plane The registers in R Plane are write only The MOVWR instruction copy the W register s content to R Plane registers by direct addressing mode The lower locations of F Plane are reserved for the SFR Above the SFR is General P...

Page 11: ...changed The STACK is 10 bit wide and 5 level in depth The CALL instruction and hardware interrupt will push STACK level in order While the RET RETI RETLW instruction pops the STACK level in order 1 4 ALU and Working W Register The ALU is 8 bit wide and capable of addition subtraction shift and logical operations In two operand instructions typically one operand is the W register which is an 8 bit ...

Page 12: ...ffect those bits STATUS Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Value 0 0 0 0 0 0 R W R W R R R W R W R W Bit Description 7 Not Used 6 General Purpose Bit 5 Not Used 4 TO Time Out 0 after Power On Reset LVR Reset or CLRWDT SLEEP instruction 1 WDT time out occurs 3 PD Power Down 0 after Power On Reset LVR Reset or CLRWDT instruction 1 after SLEEP instruction 2 Z Zero Flag 0 the result...

Page 13: ...by F W If the corresponding interrupt enable bit has been set INTE it would trigger CPU to service the interrupt CPU accepts interrupt in the end of current executed instruction cycle In the mean while a CALL 001 instruction is inserted to CPU and i flag is set to prevent recursive interrupt nesting The i flag is cleared in the instruction after the RETI instruction That is at least one instructio...

Page 14: ...hreshold levels can be selected The LVR s operation mode is defined by the SYSCFG register There are two voltage selections for the LVR threshold level one is higher level which is suitable for application with VDD is more than 3 3V while another one is suitable for application with VDD is less than 3 3V See the following LVR Selection Table user must also consider the lowest operating voltage of ...

Page 15: ...d when user reads PROM Bit 13 0 Default Value 11111111111111 Bit Description 13 nPROTECT Code protection selection 1 No protect 0 Code protection 12 nREUSE PROM Re use control 1 Not Re use 0 Re use 11 10 LVR LV Reset Mode 11 LVR threshold is 1 5V always enable 10 LVR threshold is 1 5V disable in sleep mode 01 LVR threshold is 2 3V always enable 00 LVR disable 9 8 CLKS Fast Clock Source Selection 1...

Page 16: ... the compiled object code has reset vector at 200h In the SYSCFG if nPROTECT 0 and nREUSE 1 the Code protection area is first half of PROM This allows the Writer tool to write then verify the Code during the Re use Code programming After the Re use Code being written into the PROM s second half user should write nREUSE control bit to 0 In the mean while the Code protection area becomes the whole P...

Page 17: ... enable or disable the slow clock for the Timer2 system operating In this mode the program is executed using fast clock as CPU clock The Timer0 PWM0 PWM1 blocks are also driven by fast clock Timer2 can also be driven by fast clock by setting TM2CLK to 1 Slow Mode In slow mode TM57PE10 can select SXT XRC or SIRC as its CPU clock by R Plane control register SUBTYP In this mode the fast clock is stop...

Page 18: ...its to Slow Mode Fast mode can be chosen by SYSCFG 9 8 when equals to 11 Fast Crystal 00 External RC or 01 Fast Internal RC The following steps are suggested to be executed by order when fast mode transits to slow mode 1 Enable slow clock SUBE 1 2 Switch to slow clock SELSUB 1 3 Stop fast clock STPFCK 1 Slow Mode transits to Fast Mode Slow mode can be enabled by SUBE bit and SELSUB bit in CLKCTRL ...

Page 19: ...mer and Timer2 interrupt Stop Mode Setting The Stop mode can be configured by following setting in order 1 Stop slow clock SUBE 0 2 Execute SLEEP instruction Stop mode can be woken up by XINT PAWKUP PBWAKP and Wake up Timer IO setting note in dual clock mode Note In slow clock modes PA3 and PA4 must be set as input pull up mode when slow clock selects SXT or XRC mode PA3 and PA4 IO setting list is...

Page 20: ...stops for power saving In other words user keeps the WDT WKT alive in Sleep Mode by setting WKTIE 1 If the WDTE 1 and WKTIE 0 WDT WKT timer will be cleared and stopped to power saving in sleep mode If the WDTE 1 and WKTIE 1 WDT WKT timer keeps counting in sleep normal mode Refer to the following table and figure nRESET XRSTE Power On Reset Low Voltage Detector WKTIE 4 WDTE EN Watchdog RC OSC WDTE ...

Page 21: ...le TM0PSC register in R Plane The Timer0 can generate interrupt flag TM0I when it rolls over 8 BIT TIMER0 8 BIT PRESCALER SYNC TOIEDGE 1 0 Fosc 2 T0I TM0IE Timer0 Overflow Interrupt TM0I DATA BUS SELT0I M U X TM0PSC 3 0 4 8 8 7 8 9 0 1 2 3 4 0 1 CPUCLK INST CYCLE TM0PSC_WR TM0_WR PRESCALER TM0CLK 3 TM0PSC 3 0 TIMER0 7 0 TM0I k k 1 FF 2 00 k 1 k 2 1 Write 0xFF to TIMER0 Timer0 interrupt frequency b...

Page 22: ...t PWM The chip has a built in 8 bit PWM generator The source clock comes from Fosc divided by 1 2 4 and 8 The PWM0 duty cycle can be changed with writing to PWM0DUTY writing to PWM0DUTY will not change the current PWM0 duty until the current PWM0 period completes When current PWM0 period is finish the new value of PWM0DUTY will be updated to the PWM0BUF The PWM0 will be output to PA1 if PWM0E is s...

Page 23: ...greater than or equals to PWM0BUF PWM0CNT keeps counting up when equals to PWM0PERIOD the PWM0 output is set to 1 again PWM0PERIOD PWM0CNT XX YY ZZ PWM0DUTY PWM0BUF XX YY ZZ PWM0O CLRPWM0 PWM0BUF FOSC FOSC 2 PWM0PSC 01 K K 1 PWM0 output duty PWM0DUTY PWM0PERIOD 1 When PWM0DUTY 80H PWM0PERIOD FFH PWM0 output duty will be 1 2 PWM0 output frequency Fosc div PWM0PERIOD 1 Note The div variable represen...

Page 24: ...ister The output of PWM1 shares the pin PB5 that can be selected by PWM1E control bit Figure is the block diagram of PWM1 PWM1CNT A B A B System RESET Fosc 8 00H 8 R S A B A B PWM1DUTY 0 1 Q PBO 5 PB5 PWM1E PWM1DUTY PWM1CNT 255 PWM1DUTY Tosc Tosc PWM1 PWM1CNT 0 256 Tosc CPUCLK PWM1CNT PWM1CNT is internal counter that cannot be read by instruction PWM1 output duty PWM1DUTY 256 When PWM1DUTY 80H PWM...

Page 25: ...ing CMPOE which in R plane 17H Bit5 The analog comparator can generate interrupt CMPI when the output status changes The user can select interrupt triggering on comparator output rise or fall The input source of negative pin can be selected from IN0 or IN0 by CMPINNS The analog comparator supports internal reference voltage The internal reference voltage provides the range of output voltage with 1...

Page 26: ...rnal RC mode the external resistor and capacitor determine the oscillation frequency In the fast internal RC mode the on chip oscillator generates 4 8 MHz system clock In this mode PCB Layout may have strong effect on the stability of Internal Clock Oscillator Since power noise degrades the performance of Internal Clock Oscillator placing power supply bypass capacitors 1 uF and 0 1 uF very close t...

Page 27: ...e is that the output rise time can be much faster than pure open drain structure S W sets PAE 1 to use the pin in CMOS push pull output mode Reading the pin data PAD has different meaning In Read Modify Write instruction CPU actually reads the output data register In the other instructions CPU reads the pin state The so called Read Modify Write instruction includes BSF BCF and all instructions usi...

Page 28: ...in mode instead D Q D Q D Q WR_PxD WR_PxE DATA Write Pin PxE SN RN SYS_RESE Tn RN WR_nPxPU nPxPU 1 0 RD_PxD Read_Modify_Write Rpull up PxD Port Pre Driver MP MR MN DATA Read 4 3 PA7 PA7 can be only used in Schmitt trigger input mode The pull up resistor is always connected to this pin D Q WR_PAD DATA Write Pin SN SYS_RESETn 1 0 RD_PAD Read_Modify_Write Rpull up PAD DATA Read MN Drive PxE PxD PA3 6...

Page 29: ...0 Timer2 interrupt enable 1 enable 0 disable CMPIE 08 5 R W 0 Comparator interrupt enable 1 enable 0 disable TM0IE 08 4 R W 0 Timer0 interrupt enable 1 enable 0 disable WKTIE 08 3 R W 0 Wakeup Timer interrupt enable 1 enable 0 disable XINT2E 08 2 R W 0 INT2 pin interrupt enable 1 enable 0 disable XINT1E 08 1 R W 0 INT1 pin interrupt enable 1 enable 0 disable XINT0E 08 0 R W 0 INT0 pin interrupt en...

Page 30: ... flag set by H W at INT0 pin s f r edge W 0 write 0 clear this flag write 1 no action PWM0DUTY 12 7 0 R W 0 PWM0 duty PWM1DUTY 13 7 0 R W 0 PWM1 duty SELSUB 14 7 R W 0 Select slow clock as CPUCLK STPFCK 14 6 R W 0 Stop fast clock SUBE 14 5 R W 0 Slow clock enable 14 4 Reserved CMPST 14 3 R Comparator output status CLRTM2 14 2 R W 0 Write 1 to clear Timer2 auto cleared by H W STOPTM0 14 1 R W 0 Sto...

Page 31: ... or Schmitt trigger input 1 the pin is CMOS push pull output nPAPU 08 6 0 W 7F 0 the pin pull up resistor is enabled except a the pin s output data register PAD is 0 b the pin s CMOS push pull mode is chosen PAE 1 c the pin is working for Crystal or external RC oscillation 1 the pin pull up resistor is disabled nPBPU 09 7 0 W FF 0 the pin pull up resistor is enabled 1 the pin pull up resistor is d...

Page 32: ...4 W 0 Timer2 clock source 0 slow clock 1 CPUCLK 128 TM2DIV 14 3 2 W 0 Timer2 interrupt is Timer2 clock divide by 0 32768 1 16384 2 8192 3 128 SUBTYP 14 1 0 W 0 Slow clock type 0 SXT 1 SIRC 2 XRC CMPEN 17 7 W 0 Comparator enable CMPEDGE 17 6 W 0 0 Comparator falling edge to trigger interrupt event 1 Comparator rising edge to trigger interrupt event CMPOE 17 5 W 0 Comparator output to pin enable CMP...

Page 33: ...stination designator specifies where the result of the operation is to be placed If d is 0 the result is placed in the W register If d is 1 the result is placed in the address specified in the instruction For bit oriented instructions b represents a bit field designator which selects the number of the bit affected by the operation while f represents the address designator For literal operations k ...

Page 34: ... ffff 1 C DC Z Subtract W from f SWAPF f d 00 1110 dfff ffff 1 Swap nibbles in f TESTZ f 00 1000 1fff ffff 1 Z Test if f is zero XORWF f d 00 0110 dfff ffff 1 Z XOR W with f Bit Oriented File Register Instruction BCF f b 01 000b bbff ffff 1 Clear b bit of f BSF f b 01 001b bbff ffff 1 Set b bit of f BTFSC f b 01 010b bbff ffff 1 or 2 Test b bit of f skip if clear BTFSS f b 01 011b bbff ffff 1 or 2...

Page 35: ...If d is 0 the result is stored in the W register If d is 1 the result is stored back in register f Cycle 1 Example ADDWF FSR 0 B W 0x17 FSR 0xC2 A W 0xD9 FSR 0xC2 ANDLW Logical AND Literal k with W Syntax ANDLW k Operands k 00h FFh Operation W W AND k Status Affected Z OP Code 01 1011 kkkk kkkk Description The contents of W register are AND ed with the eight bit literal k The result is placed in t...

Page 36: ...if f b 0 Status Affected OP Code 01 010b bbff ffff Description If bit b in register f is 1 then the next instruction is executed If bit b in register f is 0 then the next instruction is discarded and a NOP is executed instead making this a 2nd cycle instruction Cycle 1 or 2 Example LABEL1 BTFSC FLAG 1 TRUE GOTO SUB1 FALSE B PC LABEL1 A if FLAG 1 0 PC FALSE if FLAG 1 1 PC TRUE BTFSS Test b bit of f...

Page 37: ...CLRF Clear f Syntax CLRF f Operands f 00h 7Fh Operation f 00h Z 1 Status Affected Z OP Code 00 0001 1fff ffff Description The contents of register f are cleared and the Z bit is set Cycle 1 Example CLRF FLAG_REG B FLAG_REG 0x5A A FLAG_REG 0x00 Z 1 CLRW Clear W Syntax CLRW Operands Operation W 00h Z 1 Status Affected Z OP Code 00 0001 0100 0000 Description W register is cleared and Z bit is set Cyc...

Page 38: ...B CNT 0x01 Z 0 A CNT 0x00 Z 1 DECFSZ Decrement f Skip if 0 Syntax DECFSZ f d Operands f 00h 7Fh d 0 1 Operation destination f 1 skip next instruction if result is 0 Status Affected OP Code 00 1011 dfff ffff Description The contents of register f are decremented If d is 0 the result is placed in the W register If d is 1 the result is placed back in register f If the result is 1 the next instruction...

Page 39: ...ced back in register f If the result is 1 the next instruction is executed If the result is 0 a NOP is executed instead making it a 2 cycle instruction Cycle 1 or 2 Example LABEL1 INCFSZ CNT 1 GOTO LOOP CONTINUE B PC LABEL1 A CNT CNT 1 if CNT 0 PC CONTINUE if CNT 0 PC LABEL1 1 IORLW Inclusive OR Literal with W Syntax IORLW k Operands k 00h FFh Operation W W OR k Status Affected Z OP Code 01 1010 k...

Page 40: ...fected OP Code 01 1001 kkkk kkkk Description The eight bit literal k is loaded into W register The don t cares will assemble as 0 s Cycle 1 Example MOVLW 0x5A B W A W 0x5A MOVWF Move W to f Syntax MOVWF f Operands f 00h 7Fh Operation f W Status Affected OP Code 00 0000 1fff ffff Description Move data from W register to register f Cycle 1 Example MOVWF REG1 B REG1 0xFF W 0x4F A REG1 0x4F W 0x4F MOV...

Page 41: ...e 2 Example RET A PC TOS RETI Return from Interrupt Syntax RETI Operands Operation PC TOS GIE 1 Status Affected OP Code 00 0000 0110 0000 Description Return from Interrupt Stack is POPed and Top of Stack TOS is loaded in to the PC Interrupts are enabled This is a two cycle instruction Cycle 2 Example RETI A PC TOS GIE 1 RETLW Return with Literal in W Syntax RETLW k Operands k 00h FFh Operation PC ...

Page 42: ...1 1110 0110 C 0 A REG1 1110 0110 W 1100 1100 C 1 RRF Rotate Right f through Carry Syntax RRF f d Operands f 00h 7Fh d 0 1 Operation C Register f Status Affected C OP Code 00 1100 dfff ffff Description The contents of register f are rotated one bit to the right through the Carry Flag If d is 0 the result is placed in the W register If d is 1 the result is placed back in register f Cycle 1 Example R...

Page 43: ...REG1 0x02 W 0x02 C Z A REG1 0x00 W 0x02 C 1 Z 1 B REG1 0x01 W 0x02 C Z A REG1 0xFF W 0x02 C 0 Z 0 SWAPF Swap Nibbles in f Syntax SWAPF f d Operands f 00h 7Fh d 0 1 Operation destination 7 4 f 3 0 destination 3 0 f 7 4 Status Affected OP Code 00 1110 dfff ffff Description The upper and lower nibbles of register f are exchanged If d is 0 the result is placed in W register If d is 1 the result is pla...

Page 44: ...ed with the eight bit literal k The result is placed in the W register Cycle 1 Example XORLW 0xAF B W 0xB5 A W 0x1A XORWF Exclusive OR W with f Syntax XORWF f d Operands f 00h 7Fh d 0 1 Operation destination W XOR f Status Affected Z OP Code 00 0110 dfff ffff Description Exclusive OR the contents of the W register with register f If d is 0 the result is stored in the W register If d is 1 the resul...

Page 45: ...TA 25 C Parameter Rating Unit Supply voltage VSS 0 3 to VSS 6 5 V Input voltage VSS 0 3 to VDD 0 3 Output voltage VSS 0 3 to VDD 0 3 Output current high per 1 PIN 25 mA Output current high per all PIN 80 Output current low per 1 PIN 30 Output current low per all PIN 150 Maximum Operating Voltage 5 5 V Operating temperature 40 to 85 C Storage temperature 65 to 150 ...

Page 46: ... Input except PA7 VDD 5V 0 2VDD V VDD 3V 0 2VDD V PA7 VDD 5V 0 2VDD V VDD 3V 0 2VDD V Output High Voltage VOH All Output VDD 5V IOH 8 mA 4 4 V VDD 3V IOH 4 mA 2 6 V Output Low Voltage VOL All Output VDD 5V IOL 20 mA 0 5 V VDD 3V IOL 10 mA 0 3 V Input Leakage Current pin high IILH All Input VIN VDD 1 µA Input Leakage Current pin low IILL All Input VIN 0 V 1 µA Supply Current IDD Fast mode LVR enabl...

Page 47: ... 32 KHz 9 5 VDD 3V SXT 32 KHz 2 2 VDD 5V SIRC 8 2 VDD 3V SIRC 1 8 Stop mode LVR enable VDD 5V 0 9 VDD 3V 0 5 Stop mode LVR disable VDD 5V 0 1 VDD 3V 0 1 System Clock Frequency FOSC VDD LVRth VDD 5V 24 MHz VDD 3V 24 VDD 2 4V 20 VDD 2V 12 VDD 1 5V 6 LVR Reference Voltage VLVR 1 5 V 2 3 LVR Hysteresis Voltage VHYST 0 1 V Low Voltage Detection time tLVR 100 µs Pull Up Resistor RP VIN 0 V Ports A B VDD...

Page 48: ...pF 3 6 R 10K C 100 pF 0 7 R 100K C 100 pF 0 08 Fast Internal RC Frequency 25 C VDD 3 5 5V 7 75 8 8 25 25 C VDD 2 6 3V 7 6 8 8 4 40 C 85 C VDD 2 6 5 5V 7 5 8 8 5 4 Reset Timing Characteristics TA 40 C to 85 C VDD 5V Parameter Conditions Min Typ Max Unit RESET Input Low width Input VDD 5V 10 3 µs WDT wakeup time VDD 5V WKTPSC 00 14 ms VDD 3V WKTPSC 00 18 CPU start up time VDD 5V 3 5 ms 6 Characteris...

Page 49: ...y Rev 1 4 2012 01 19 WDT WKT TimeOut vs Temperature 0 5 10 15 20 25 30 40 20 0 20 30 50 70 85 ms 2 5V 3V 4V 5V 5 5V LVR vs Temperature 0 0 0 5 1 0 1 5 2 0 2 5 3 0 40 20 0 20 30 50 70 85 V LV 2 3V LV 1 5V FIRC Freq vs Voltage 7 2 7 4 7 6 7 8 8 0 8 2 8 4 8 6 2 5 3 4 5 5 5 V MHz 40 0 25 50 85 ...

Page 50: ...Information UM TM57PE10_E 8 Bit Microcontroller 50 tenx technology inc Preliminary Rev 1 4 2012 01 19 FIRC Freq vs Temperature 7 2 7 4 7 6 7 8 8 0 8 2 8 4 8 6 40 20 0 20 30 50 70 85 MHz 2 5V 3 0V 4 0V 5 0V 5 5V ...

Page 51: ... OTP Wafer Dice blank chip TM57PE10 COD Wafer Dice with code TM57PE10 OTP 02 X DIP 14 pin 300 mil TM57PE10 OTP 15 X SOP 14 pin 150 mil TM57PE10 OTP 03 X DIP 16 pin 300 mil TM57PE10 OTP 16 X SOP 16 pin 150 mil TM57PE10 OTP 04 X DIP 18 pin 300 mil TM57PE10 OTP 20 X SOP 18 pin 300 mil Note X represents the package material Package material Pb free Code W Package material Green Package Code G ...

Page 52: ... 2 54 0 100 eB C 0 25 0 33 0 010 B1 1 27 1 52 1 78 0 050 0 060 0 013 0 015 0 180 0 46 Title P DIP 14L Package Outline Drawing 1 19 1 32 0 047 0 052 E1 B B1 e D1 A2 A1 A L D 3 25 0 128 14 SOP Package Dimension MAX INCHES MILLIMETERS MAX SYMBOL A MIN MIN 1 75 A1 A2 1 50 B 0 33 0 51 0 013 NOM 1 45 NOM 0 057 0 059 0 020 0 10 0 010 8 55 0 063 e E 3 80 4 00 0 150 0 157 H 5 80 6 20 0 228 L 0 40 1 27 0 01...

Page 53: ...Advance Information UM TM57PE10_E 8 Bit Microcontroller 53 tenx technology inc Preliminary Rev 1 4 2012 01 19 16 DIP Package Dimension ...

Page 54: ...Advance Information UM TM57PE10_E 8 Bit Microcontroller 54 tenx technology inc Preliminary Rev 1 4 2012 01 19 16 SOP Package Dimension ...

Page 55: ... 23 11 0 894 0 904 22 96 0 910 E 7 62 8 26 0 300 E1 6 40 6 65 0 252 0 256 e 3 18 8 38 6 50 0 125 9 65 0 325 0 262 0 330 L 0 43 0 017 2 54 0 100 eB C 0 25 0 33 0 010 B1 1 27 1 52 1 78 0 050 0 060 0 013 0 015 0 180 0 46 Title P DIP 18L Package Outline Drawing 0 56 0 69 0 022 0 027 18 SOP Package Dimension 1 27 1 041 0 025 2 337 0 05 2 515 0 1 0 1778 0 05 0 406 0 508 x 45 0 762 0 076 15 5 0 254 0 05 ...

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