Telos Alliance LINEAR ACOUSTIC ARC, Installation & User Manual

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Chapter 3 |
6
I/O, Clocking and Reference
Reference Clocking and Sample Rate Converters
Because ARC’s signal routing is so flexible and it supports multiple input and output formats, having a firm grasp of the clock
sync (reference) requirements is critical. Some basics to remember:
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Sample Rate Converters (SRCs) are provided on the SDI input, SDI output, and AES-3 input; the AES-3 output is always
synced to the active reference clock; There are no SRCs in the AES67 path.
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Reference clock source options include:
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Internal 48kHz
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SDI Input
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AES-3 Input
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PTP v2 per AES67-2015
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When all input sources are SDI and the outputs are routed to the embedded SDI output, the reference signal present on
the SDI input must be used
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When using AES-3 I/O, ARC can be referenced to either the AES-3 clock (using the SRCs in the SDI path) or to the SDI
clock (using the SRCs in the AES-3 path)
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When using an AES-3 source without an accompanying reference, ARC’s 48kHz internal clock can be used as the system
reference if necessary, providing the SRC on the AES-3 input is enabled
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Whenever AES67 audio is used either on the input, the output, or both, ARC must be slaved to an externally-generated
PTP clock as it cannot generate its own; details on PTP settings are provided in Chapter 5 under “System Menu”.
Important:
All audio pairs are de-embedded at the input and then re-embedded at the output when using the SDI
I/O. While ARC accepts only PCM audio for processing, if there is any coded audio present on any of the SDI
audio pairs, the SDI SRCs must be turned off as the coded audio bitstream will become corrupted if passed
through an SRC.