L
LE920 Hardware User Guide
1vv0301026 Rev.0 - draft4 – 2013-05-
Reproduction forbidden without written authorization from Telit Communications S.p.A. - All Rights Reserved.
Page 57 of 76
11.1.
Logic Level Specifications
Where not specifically stated, all the interface circuits work at 1.8V CMOS logic levels.
The following table shows the logic level specifications used in the LE920 interface circuits:
For 1,8V signals:
Absolute Maximum Ratings -Not Functional
Parameter
LE920
Min
Max
Input level on any
digital pin when on
-0.3V
+2.16 V
Input voltage on
analog pins when on
-0.3V
+2.16 V
Operating Range - Interface levels (1.8V CMOS)
Level
LE920
Min
Max
Input high level
1.5V
2.1V
Input low level
-0.3V
0.5V
Output high level
1.35V
1.8V
Output low level
0V
0.45V
11.2.
Using a GPIO Pad as Input
The GPIO pads, when used as inputs, can be connected to a digital output of another device
and report its status, provided this device has interface levels compatible with the 1.8V
CMOS levels of the GPIO.
If the digital output of the device is connected with the GPIO input, the pad has interface
levels different from the 1.8V CMOS. It can be buffered with an open collector transistor with
%'?Q-up resistor to 1.8V.
