Q-Lite Satellite Modem Installation and Operating Handbook
9-2
Q3001 LVDS Interface
The LVDS interface is used as follows.
Min
Req
Signal Description
LVDS
Name
Circuit
Number
25 pin
Electrical
Levels
A
B
DATA CIRCUIT TOWARDS MODEM (TX)
Clock In
TT
113
24
11
LVDS
Data In
SD
103
2
14
LVDS
Sig
’
Valid In
RS
105
4
19
LVDS
Sig Accpt
’
d Out
CS
106
5
13
LVDS
Int
’
Tx Clock Out
ST
114
15
12
LVDS
DATA CIRCUIT FROM MODEM (RX)
Clock Out
RT
115
17
9
LVDS
Data Out
RD
104
3
16
LVDS
Sig
’
Valid Out
RR
109
8
10
LVDS
COMMON LINES
Signal Ground
SG
102
7
Ground
Shield/Protective ground
PG
101
1
Screen
Device (DTE) Ready In
TR
108
20
23
LVDS
Device (DCE) Ready Out
DM
107
6
22
LVDS
Local Loop In
LL
141
18
LVDS
Remote Loop In
RL
140
21
LVDS
The modem can operate at high data rates using the LVDS interface, but the maximum
useable data rate is limited by connecting cable length. The maximum data rate
is 10Mbps
over a 10m cable (over good quality twisted pair screened cable), but this rate is reduced
as the connecting cables extend beyond 10m. As an estimate, assume the maximum rate
halves as the distance doubles (.e. 5Mbps to 20m, 2.5Mbps to 40m etc). Similarly, the
maximum data rate increases as the connecting cable length is reduced (i.e. 20Mbps to
5m, 40Mbps to 2.5m).
The input clock/data phase is selected automatically, reporting a `Data Marginal` warning
whenever it has to switch phase. If the modem reports Data Marginal frequently then this is
not a modem fault but an indication that you have a clocking problem external to the
modem (ie changing clock/data phase, a problem which would otherwise have caused
untraceable data errors). With the Tx Clocking Set to
Tx Clock In
the `Data In` signal is
checked against the `Clock In` signal. With the Tx Clocking Set to
Internal
or
Rx
the `Data
In` signal is checked against the `Int` Tx Clk Out` signal.
