U
SER
M
ANUAL
8
K
/4
K
CL
M
ONO
–
R
EV
I
–
06/2017
P
A G E
|
8
2.2
Image Sensor
The 8k sensor is composed of two
pairs of sensitive lines. Each pair of lines use
the same Analog to Digital Column converter
(ADC Column). An appropriate (embedded)
Time delay in the exposure between each
line allows combining two successive
exposures in order to double the sensitivity
of a single line.
This Time Delay Exposure is used only in the
4S multi-line modes (4 Lines) and also in the
three binning modes, as described below.
The 8192 Pixels of the whole sensor are
divided in 2 blocks of 4096 pixels.
2.3
Sensor modes
a
b
c
d
a
b
c
d
B
a
b
c
d
C
B
A
C
D
Mode 1S = B
Mode 2S = B+C (FPGA)
Mode 4S = (A.B)+(C.D)
Note : (A.B) = summation in the
sensor (
not available for
EV71YC2MCL8005-BAx
)
8K Pixels Output
a
b
c
d
a
b
c
d
A
A
B
Mode 1SB = A
Mode 2SB = (A+B)
4k Pixels Output
ADC Column
ADC Column
Memory Node
Pixel Line A
Pixel Line B
Pixel Line C
Pixel Line D
Memory Node
a
b
c
d
A
Mode 4SB = A
2k Pixels Output
