U
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ANUAL
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Structure of the Sensor
In 2S Mode, the summation
of the two lines is done in
the FPGA :
B+C
In 4S Mode, the summation
of the two double lines is
done in the FPGA :
(AB )+ (BC)
This mode works in “Time delay exposure” for the summation of each double line in the
sensor.
Binning modes
The two binning modes 1SB and 2SB give an output of 4k pixels 10x10µm.
As for the 2SB mode, the sensor manages the delay between the two exposures necessary
for a “good match” acquisition.
The 4SB is a binning 4x4 with an output of 2K pixels 20x20µm
Rectangular Pixels : Sensor Delay Top/Bottom
In addition to these Sensor modes, the Delay between the Top and The Bottom of the
Sensor (when both are used : Modes 2S, 4S, 2SB) can be disabled in order to get Rectangular
Pixels with the following equivalence :
2S (x2 5x5µm) => x1 Pixel 5x10µm
4S (x4 5x5µm) => x2 Pixels 5x10µm
2SB (x2 10x10µm) => x1 Pixel 10x20µm
ADC
Colum
ADC
Colu
Memory Node
Pixel Line A
Pixel Line B
Pixel Line C
Pixel Line D
Memory Node
Web Direction
2S
1S
4S
Exposure
delays
FPGA
ADC
ADC
Memory Node
Pixel Line A
Pixel Line B
Pixel Line C
Pixel Line D
Memory Node
Web Direction
1SB
Exposure
Delay
2SB
2SB
4SB
