Teledyne LeCroy
PCI Express Mid-Bus Probe for Summit Analyzers
Version 1.1
5
2 Probe Components
Universal Retention Module (
B
)
Mid-Bus Probe Header Cable Assembly
(D)
Mid-Bus Probe Pod
(C)
Analyzer Cable
(E)
Power adapter for the Probe Pod (
F
)
Clocking Cable Assembly (not shown)
The Intel-based mid-bus footprint specification only supplies differential lane signaling and ground reference. Should a
reference clock (RefClk) be required a separate connection must be made. Teledyne LeCroy PCI Express protocol
analyzers can use a reference clock probe in conjunction with the mid-bus analysis. Each mid-bus probe is equipped with
one clock probe. The mid-bus reference clock probe is designed to facilitate capturing clock signals from the system
board in the two configurations recommended by the Intel guideline, i.e., a tap off of an existing clock or a dedicated clock.
PCI Express target board (A) with Mid-Bus Probe (B, C and D)