Tektronix P7001 /IEEE 488 Instruction Manual Download | Manualshive

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Summary of Contents for P7001 /IEEE 488

Page 1: ...CHECK FOR CHANGE INFORMATION AT THE REAR OF THIS MANUAL P7001 EEE 488 INTERFACE 021 0206 00 INSTRUCTION MANUAL Tektronix Inc PO Box 500 Beaverton Oregon 97077 Serial Number 070 2623 00 First Printing JUL 1978 Product Group 45 Revised DEC 1986 ...

Page 2: ...rice change privileges are reserved INSTRUMENT SERIAL NUMBERS Each instrument has a serial number on a panel insert tag or stamped on the chassis The first number or letter designates the country of manufacture The last five digits of the serial number are assigned sequentially and are unique to each instrument Those manufactured in the United States have six unique digits The country of manufactu...

Page 3: ... Device Address Switch SW412 2 1 Setting The P123 Strap Option 2 2 P7001 IEEE 488 Interface Installation 2 3 IEEE 488 Bus Connector Pin Assignments 2 4 3 5 3 8 3 9 Data Transfer Delimiters Terminators P7001 4K Memory Map DPO Card Address Map Location of Readout Words and Characters WWWL ONNN waI DWN Timeslots and Field 0 Addresses 3 12 3 5 Status Word Formats 3 14 3 6 HSA Status Register Bit Assig...

Page 4: ...262531 P7001 IEEE 488 INTERFACE ...

Page 5: ...ces and incIudes a system controIIer such as a Tektronix 4051 Graphic System as weII as taIkers and Iisteners The DPO in such a system functions as both a taIker and a Iistener As a talker the DPO sends current status messages data captured by the Acquisition Unit and readout information to the system controIIer or other system Iisteners As a Iistener it receives commands and data from the system ...

Page 6: ...r Handshake AH TaIker T Listener L Service Request SR Remote LocaI RL ParaIIeI PoII pP Device CIear DC Device Trigger DT ControIIer C IEEE Std 488 Section 10 11 12 Interface CapabiIity CompIete SH1 CompIete AH1 No TaIk Only Mode T6 No Listen OnIy Mode L4 CompIete SR1 None RLﬂ N0ne PP None DCQ None DTg None cg 1 2 ...

Page 7: ...y be installed in a P7001 Proces sor using the instructional steps listed on the Installation Diagram Figure 2 3 Before the interface is installed however the IEEE 488 Bus Device Ad dress and the P123 Strap Option should be set as explained in the following paragraphs SELECTING DEVICE ADDRESS Selecting the Device Address is accomplished by setting the 5 bit DIP switch SN412 0n the MPU GPIB board s...

Page 8: ...e P123 strap option allows the interface to operate more efficiently with different controllers A more thorough explanation of use of the strap option may be found in Section 3 of this manual Figure 2 2 shows connector P123 set for both Standard operation jumper not installed and Optional operation pin 1 jumpered to adjacent pin pin 1 is indicated withu P123633 2 g 81 P123 ﬁg m 8 73 I a a a a Eﬂiﬂ...

Page 9: ...00l IEEE 488 Interface Interface Installation Screws 2 Cable Assy 012 0630 01 SW412 Behind Side Panel With AC power off insert the interface into the rear of the P7001 Processor and press in slowly until the assembly is firmly seated 012 0630 01 to the interface assembly at J1 and secure with thumb screws terface installation screws and thumbscrews are fully disengaged 2623 04 Figure 2 3 P7001 IEE...

Page 10: ... 488 compatible device Figure 2 4 shows the con nector pin arrangement and signal line nomenclature The interface also includes the mating connector and cable Tektronix Part No 012 0630 01 standard 2 meter IEEE 488 cable This connector is double sided with a male side to mate with the connector on the interface and a female side for connecting additional system components to the bus SHIELD SRO NDA...

Page 11: ...P7001 bus of a Tektronix Digital Processing Os cilloscope 0P0 There are three different types of devices on the IEEE 488 bus controllers talkers and listeners IEEE Standard 488 1975 allows specific listeners and talkers to be selected and de selected inde pendently The responsibility of the controller is to designate which sys tem connected instruments are to listen or to talk The DPO in such a sy...

Page 12: ...powered up 82 DPO was hung but has self corrected 83 DPO PROGRAM CALL button pushed 84 DPO Single Sweep completed 85 HSA aborted if HSA is installed 18 Error has occurred see following para graph entitled Error Messages Error Messages Four different error conditions may exist for the DPO each will be in dicated to the system controller by an SRQ A status poll conducted after receipt of the SRQ wil...

Page 13: ...s been assigned device address 1 the 4051 will continue to poll devices in the order shown until it reaches device 1 When the 4051 finds that device 1 issued the SRQ it assigns the number _to variable N in the POLL statement because device 1 is the third device on the list The DPO returns a decimal status word previously explained which is assigned to the variable M Line 51 causes N and M to be pr...

Page 14: ... illustrated in Sec tion 2 of this manual The option provides two operating modes Standard operation and Optional operation Standard operation is defined as be tween the DPO and a Tektronix controller such as the TEK 4051 Optional operation should be used with Hewlett Packard controllers such as the HP 9825 to speed up transfer time use less core and ease programming Delimiters and terminators use...

Page 15: ...re ceive data listen respectively MTA and MLA are identical to the I O Address referred to in the TEK 4051 manual and may col lectively be referred to as Hardware Unit Number HUN or Device Address Instructions for setting this address are in Section 2 of this manual DAB Command Data Bytes consist of three data bytes of ASCII characters followed by either a question mark or a blank space both also ...

Page 16: ...T SCL SSR STO TAB TAC TAD TBA TBC TBD TCA TCB Address Channel Clear F Data Device C Waveform Waveform B of DPO Memory is selected Waveform Waveform D of DPO Memory is selected Hardware Histogra Hold Octal Scale Fa Single Sweep Reset Store Transfer Transfer Transfer Transfer Transfer Transfer Transfer Transfer Transfer Transfer Transfer Transfer Word Set DPO Set DPO Page 3 9 3 11 ront Panel Interru...

Page 17: ...Data DPA Send Waveform A of DPO memory DPB Send Waveform B of DPO memory DPC Send Waveform C of DPO memory DPD Send Waveform D of DPO memory wwwwwwwwww I Hl l l KOKDKOLDI IKO FPI Front Panel Interrupt 9 OCT Octal 6 SCL Scale Factor 1 WRD Word 1 DATA TRANSFER The DPO memory contains four waveform locations designated A B C and D Each waveform is a 512 element array The data for each element is an i...

Page 18: ...r Store and llHold operations in the DPD Store and Hold operations may be performed using the STOb and HOLb commands explained later or may be executed manually from the DPO Front Panel see DPO Operators Manual Tektronix P N 070 1599 00 A single blank space after the command mnemonic such as DPAb or DPCb indicates a data transfer from the TEK 4051 to the DPD The command is de limited with a semico...

Page 19: ...ently The addressable DPO memory is from decimal 0 to 8191 See Figure 3 2 P7001 4K Memory Map and Figure 3 3 DPO Card Address Map The following TEK 4051 example shows Device Address 1 the DPO ad dress 2560 the start of Field 1 being selected PRINT 1 ADR 2560 Note that the argument following the command mnemonic 2560 in the above ex ample may also be a numeric variable that is defined elsewhere in ...

Page 20: ...f the second half of Waveform A see Figure 3 2 line 12 readies the DPO to talk and line 13D transfers the 512 data words from the DPO to the controller After completion of this sequence array X is holding the second half of Waveform A and the first half of Waveform B IOD DIM X 512 11 PRINT 1 ADR 256 12D PRINT 1 DAT 13 INPUT 1 X WRD Commands The WRD word commands allow the 10 bits of a DPO data wor...

Page 21: ...ons Fields 1 2 and 3 are used mainly for displaying messages Each field has four designated areas for Waveforms A B C and D as shown on Figure 3 2 Also shown are the addresses for each of the waveforms in the four fields e g waveform C of field 2 uses addresses 3328 3407 Each waveform in a Field has 80 displayable positions These 80 posi tions are grouped in 8 channels each with 10 displayable cha...

Page 22: ... LEFT VENT RIGHY VENT A NONI I a HOHIZ i PLUGJN NEAnouT_ LEFT VENT NICHT VENT A HONIz i a menu wOND POSITIONS CHANNEL I 5 CHANNELI CHANNELI E CHANNELI I wono POSITIONS C I i 1 c 1 I r I 1 i x i _I L I I L I I TIME SLOTS pIlzl ltlslsH aialm I121 IHsTsE IlaHui IHEIIXSISITIBI 91 IIZIJI FI I T 5 9 0 TIME SLOTS JIIJI hlGIIll 91ml I JHIIIE 11 19 IlzlaltlstI slIa IHJHSIG IlaTa In 1 A FIELDO 23 4_2313 231...

Page 23: ...out Interface Register and other DPO Registers is explained in greater detail in subsequent paragraphs Line 139 sets up the Readout Interface to display the message residing at Field 2 Waveform D 190 PRINT 1 ADR 3456 11 PRINT 1 SCL TEKTRONIX STILL MAKES THE BEST OSCILLOSCOPES 12 PRINT 1 ADR 7296 13 PRINT 1 0CT Q40100 NOTE This command does not set other registers A D Converter Display Generator Fr...

Page 24: ... THE DATA BUS WITHIN 8uS INTERRUPT TO CPU a Front Panel Status word Format Address 7424 I r 1 BIlNumbur I15 Nilallll llllﬂils 517161514 2 I El MODE n NOLD II STORE ll SEND n RECEIVE 1 I one b A D Converter Status word Format Address 7168 L I I N mwl slulurnlnI laI7l l5l lalzl l l DIQLAYGENERAYOH MODE I V T I X V MODE W HOLD ll STORE I SEND II RECEIVE WAVEFORM I A Flu e mm c II D c Display Generato...

Page 25: ... Interface Display Gen erator and Front Panel Registers is illustrated in Figure 3 5 Figure 3 6 shows the HSA status word In most cases the user does not have to learn to operate and set up these registers because the microprocessor residing in the interface takes over most of the operating procedures However there are some operations where it is necessary or desirable to control these registers b...

Page 26: ...ble that is defined elsewhere in the program The DPO Address Register in the interface will not be affected after execution of the OCTb 0r OCT commands In most cases OCT will be immediately preceded by an ADRb command to set the P7001 address on which OCT is intended to operate In the following TEK 4051 example line IQQ selects address 7 4Q Front Panel Status Register and line 11 sets the Front Pa...

Page 27: ...n of this along with a graph showing digitizing time for various combinations of sweep speed and input signal repetition rates may be found in the DPO Operators Manual Tektronix Part No 070 1599 00 starting on page 2 2 under the head ing SAMPLE HOLD and A D CONVERTER Each 4051 FOR LOOP step uses approxi mately 4 5 milliseconds Therefore lines 110 and 120 in the above example insert approximately 9...

Page 28: ...and chooses between Point and Sweep averaging The following example shows how the HAVb command is used PRINT N HAV S D M X Where N is the Device Address of the DPO and S is the source of the waveform to be averaged DPO Haveform A B C or D and D is the destination of the averaged waveform A B C or D note that S D must be followed by a space and M is a positive decimal integer from 1 to 12 for Sweep...

Page 29: ...LL button O if it is illuminated and it is desired to re enable the PROG RAM CALL buttons Previous interrupts and the CPU BUSY lamp may be cleared with the CLIO command This command has no effect on any other DPO status or memory An example of the CLIb command follows PRINT 1 CLI The following sample routine shows a way to service the UPC PROGRAM CALL buttons Note this sample routine only services...

Page 30: ...es sets to Q the DPO Address Register and sets all DPO operations with a default mode to the default mode This command can also be used to clear service requests SRQ Device Clear can be executed as follows PRINT 1 DCL Transferring Waveform Arrays Waveforms may be transferred from one DPO memory location A B C or D to another with the following command PRINT 1 TAB Where A is the waveform source can...

Page 31: ...orm in DPO memory location B Line 6O displays a message to prompt the user to set up a ground reference waveform Line 7O is simply a method to stop the controller until the user makes the necessary changes to ground the probe or plug in then he would type in a carriage return to make the program continue A would not be used in subsequent computations Lines 8O through 13O STORE HOLD and then transf...

Page 32: ...Where In 1ine 4b x 2 p1ug ins or x 4 memory or x 6 both In the foregoing exampie lines 1 through 3 acquire the current settings of the Front Panel Status Word Line 4 repiaces the two binary bits that affect the dispiay source setting and iine 5w outputs the new status word It is necessary to read the status first so that the other front panel controis do not change when the new status word is sent...

Page 33: ... QUALIFIED PERSONNEL ONLY TO AVOID PERSONAL INJURY DO NOT PERFORM ANY SERVICING OTHER THAN THAT CONTAINED IN OPERATING INSTRUCTIONS UNLESS YOU ARE QUALIFIED TO DO SO REFER TO OPERATORS SAFETY SUMMARY AND SERVICE SAFETY SUMMARY PRIOR TO PERFORMING ANY SERVICE i ...

Page 34: ......

Page 35: ...nctions and signals For further information on P7001 data and control signals see the P7001 Processor Service Manual Tektronix Part No 070 1882 00 and P7001 Main Interface Service Manual Tektronix Part No 070 1604 00 Signals associated with the MPU are explained in Motorola s M6800 Microprocessor Applications Manual and M6800 System Design Data Manual Excerpts from the latter are included as an Ap...

Page 36: ...NG DATA BUS CONTROL LINES ADDRESS LINES ADDRESS CONTROL PIA MPU BUS PROM i I L___ __ _ _ I I I I I I I I I l I I L MPU GPIB BOARD Figure 4 1 Basic BIock Diagram I I I I P7001 BUS INTERFACE LOGIC JU O I I I I I I I I I I l I I I I I I I I I I l I 512 X 8 RAM PIA P7001 BOARD m _ a _ _ 2623 0 mb_ _ ...

Page 37: ...N Attention _ 777 Interface Ciear RO Service Request Interface Management Lines REN Remote Enabie EDI End or Identify J DIOl through D108 Data Input Output Lines MPU Motoroia M6800 Bus SignaIs Refer to Figure 4 3 VMA VaIid Memory Address this MPU output indicates to the PIA s RAM and PROM that there is a vaIid address on the address bus Read when high Write when Iow this MPU output signais to the ...

Page 38: ...a Channel Request to P7001 Front Panel Priority Logic Select Acknowledge to P7001 Front Panel Priority Logic Controller Sync to P7001 Common Bus Bus Busy to from P7001 Common Bus Data Channel Grant Input from next lower priority card on P7001 common bus Data Channel Grant Output to P7001 common bus Signal from P7001 common bus engendered by DPO turn on GPIB Interface Refer to Figure 4 3 talk liste...

Page 39: ...and QXXX PEI through PE4 These are the inverted OR ed combination of decoded hexa decimal address lines XDXX through X3XX X4XX through X7XX X8XX through XBXX and XCXX through XFXX respectively They are used in conjunction with 5XXX 6XXX and 7XXX as PROM enable lines Internal Signals P7001 Bus Interface Refer to Figure 4 4 Done Signal from control logic circuitry to PIA U29 indi cates P7001 bus tra...

Page 40: ...SET When power in the DPO is first turned on the POWER EATE pulse is gener ated in the P7001 and applied from the P7001 bus to the RESET circuitry in the Interface The RESET One Shot U310 delays the pulse approximately 200 milli seconds before it releases RESET The RESET pulse accomplishes the following 1 Initializes the MPU and the PIA s 2 Under firmware control instructions stored in PROM initia...

Page 41: ...on making circuitry for the interface Operation of the MPU Microprocessing Unit or Microprocessor is quite complex and will not be analyzed to any great extent in this manual In formation regarding the MPU can be found in Motorola s M6800 Applications Man ual M6800 Microcomputer System Design Data Manual or Appendix A of this man ual The Address Decode Logic receives address lines A8 through A14 f...

Page 42: ...and control logic needed to interface the DPO s P7001 Bus to the MPU Bus timing diagrams are shown in Figures 4 2A and 4 28 When the MPU wants to read data from or write data to the DPO it first sets up the PIA s U29 for READ U27 and U28 for WRITE by programming After aIO microsecond delay to ensure that all Address lines Read Write and other control lines are settled the Enable line from U27 is a...

Page 43: ...TA CH GRANT IN SELECT ACK WSBWY dﬁﬁmitﬁr mf sVNC EEK ﬁWﬁTMmt E DONE IVOQUES P7001 IEEE Interface L__ l__ J J Figure 4 2A P7001 Bus Read Operation Cl 3 5usec max if greater than 3 5usec P7001 Bus will time out hardware error 50nsec minimum 6 Drawing not to scale Figure 4 28 P7001 Bus Write Operation 4 9 ...

Page 44: ...o the Centre Logic This sets the UPC to the id e state and terminates U U YI If one of the P7001 PROGRAM CALL buttons is pushed an T7ﬁ_ TPU E is gen erated The Contro Logic receives the T7ﬁﬁ TP5EE and interrupts the MPU via PIA U29 and the IRPT signa The MPU programs PIA U29 to ignore IRPT to dis courage continuous interrupt and ooks at the P7001 Front Pane status to determine why the T75 TPUEE wa...

Page 45: ...o n uw 359m a 3 31 9 8335 53x xxsx 5 6 E 93 I kdemm 20mm xxxu xii xxxoéxxm mmmmanZ vmnima Od om OOEZEII SEEP 4 I a 0 w w 84 rwwwx B 528 3 9 I I pom 180m 22 g 3 I I3 EMBED 5383 Ne MEAQV mo 5 I I I I 2 I EoUmzzou WWI lwx mNm _ 53 48 I I I I J cum IIIII I IEOPUmZZOU m3 323 _ Q rpmrmmﬁ 5 muwuwﬂuux 55 83 m E I mam aumz w 33 xxwx 2 u 050 2 510 H_I 5520 II F E I 5 mmmZmu z 32 adv 25 72 4 Hdu az I mmK n E...

Page 46: ... R319 34331 U118 p10 U218 U319 J U420 CR R216 R3181 JC 201L__r419T Uﬂg 217 318 U117 j 216 U c17 n c 30117 C116 ﬁ U418 U116 0216 U317 Y4l U316 C41 m 0 C41 N R41 EC U115 U U215 L315 R414 v U315 l V 3U 2U U114 9 U214 U314 m m c313c U413 58 U113 RC U213 U313 L R313 C411 D __ﬁ 3 13V SW 3 TP 412 U112 U212 U312 412 15V f c r312 0211 c r3ll U111 0211 c416 U311 RC 231811 U110 0210 4165 3R417 3C417 C 3C100 ...

Page 47: ...1 MAIN NTE RFACE ﬁ W263 Tq FROM 8025 BD7 MPu sPus Clum BOARD 19 rL c BUFFER INVERTE s fie SET A2 A1 P7001 Addrass Strobt _ __ AD ADR11 _ _ LRQAE ML __ _ _ ________ ___7 x3 x1xx VM RA EnmEle CONTROL LOGIC Plgure 4 4 PAGE 4 12 FUNCTIONAL BLOCK DIAGRAM PIA P7001 BOARD 2 78 GHVOE lOOLd Vld INVHBVICI IOO IS IVNOILONnd ...

Page 48: ... C10 U24 025 U26 U45 l44 U11 U 2 m 1 C3027 21324 8C CDC U13 U14 LEE 3 131 UM we m7 U U E323 R13 c 3c28 C29 3R24 R2 22 K 920 0 U23 UU17 U U18 C18 U44 U19 U20 U21 U22 C19 E 3 C C22 QZl C43CD U37 p20 1 U43 U36 _____ __ U39 a U35 E U U42 ﬁg C42 U34 3 p40 9 Uﬂ HARM U33 g D C4 C41 032 a C4 U31 U40 R42 U30 U38 252309 Component Location PIA P7001 Board ...

Page 49: ...I HY Hybrid circuit TP Test point BT Battery J Connector stationary portion U Assembly inseparable or non repairable C Capacitor fixed or variable K Relay integrated circuit etc CB Circuit breaker L Inductor fixed or variable V Electron tube CR Diode signal or rectifier M Meter VR Voltage regulator zener diode etc DL Delay line P Connector movable portion w Wirestrap or cable 03 Indicating device ...

Page 50: ......

Page 51: ...one 39 qu N 37 like 2 1 l5 lZl VMA 5 AA 5 IMA mail A 8097 pod co 35 10 NMI 17 MC uue 36 UVLB sa NM uno sv Wv T 5V M t C e VBcAc S 4 3 A 337 mu 39 use sa R4 gag 7 1 V55 0 14 5 11 7 377 DJ 6 H o 5 r 10 BD A 5 D 21 33 D Z K1 0 1 A3 I I 7 0 32 b 3 UBZOzm 1 A4 25 3 Em A Q 4 W 4I 5 A5 J K AC0 I l BUS s 3 5 ca 1 c 417 B BDZ _ D7 Ha WI 4 3 A7 gig A6 3 BDB 7 so D3 1 Km 5 I4 1 A 3 3 K5 ol A9 IE7 __ m A LE u...

Page 52: ... I 0 XX 1 I6 6 I Ia __ usm I 3 4 XCXX 3 usn 14Lsoo I_ _I 3 4 3 4 3 GIS 52m 26 a PE4 _ z 5 20 _ I0 6 4 D 7 0 11 H to 9 x sxx CHZ 5 ens 2 CZIZ 3 cI I my a o I o I o I 1 l9 é um 5v LV sv Z V sv Izv sv x l 9 2 I S I IeI IZI 5V 9 9 ZI V JIe I2I 5V um Z4 UH u uzm 7 4 UZIS u UHB 5V C CZJS cm 1442 WV 3 9 R Z l lﬁ I I I I 0 UZIB 55 K UIzI Lq usls UIIs s Aw 5 A tLI J I7 I s 0 II gxxx mu u 14Lsoo 3 5 3 5 3 5...

Page 53: ... s NDAC NKFD SR GND GND was 1 MCtoe LO gm P123 SV Cg 4 GND 1 5 U3I5 I3 z A oFEoRbAEr ue Gm I U7 9 m A umsm m m j UZKp E _ _ 201 DA uZl l IZ 201 IN H E_ UZZO o 5Vz 9 3 I U LtO A 1 C uus Ia 3V7 l _ ____ 3 UZIS H REM 5V 2 V 331 3VL RSH usn MC3 46 P35 K 1550 TX OUT I USED FOE EX IN TEST PURPOSES ONLY NOTE m s msmuao ONLY FOR SH 3 OPTIONAL CONTROLLER mum EET 0 3 P A S GP B TKANCENERs P O QﬂO 4 882 OO M...

Page 54: ... zo use 8 was oer Usa 4éls vss zén U a e H H uae e ls U39 4 é s 039 1 1 SV D 20 30 4D SD 9 0 14x14 b H US Naa bE 7 NSABLE B D SABLEA V DOUTB owe DOU 9 N D OUT HZ D D OUT H D NH U10 U10 0 SHEET IOFB HA DPo DATA LATCH XCVES P O 10 4853 00 P A P IOO BOARD P7OOI EEE 488 INTERFACE AS BB A8 36 A7 ECI A0 302 P IOOI MAIN MTERFACE J H A5 B5 A4 B4 A3 BB AZ BY 6 78 OHVOS ElldSIndW ...

Page 55: ...as 40 5 m A CH m In 0 DTA REG AM up no sv n5 um ____ Al m at c ACK BUS ISI H3 _ u U U9 comzoLLEEI 3 oc AH m I A S 95 _ _ a_ 4 l I ALIA I 1 I I DATA CH 1 GRANT H 0 5 I 1mm M3 kex r CEx r RM SEE DETAH I CElT Vet I A I I 5 5 013 _ I 14Lso4 RI 30 a l l 2 I I ma 3 esoPF 4 I I I TA GRAMTN BB L _________ SYNC ACK Bu OK sv a 4 n mo um Is EH U45 14 174 SEE DETAIL A SHEET 2 OF 3 DPO CONTROL FIG 670v 4 E 3 0...

Page 56: ... l1 1 9 l9 U MCQEO U41 MCQB 0 UQB MC68 O C I U11 U13 1404 14LSO4 O 3 6 H J o J LO r _ U30 U39 RESERVED oa Pumas use L __ II L______________ qiﬁ FHO JZO LP U30 ___l 2 7s to 9 MO 20 H9 95 he 7 H7 0 a I 50 HE 144 H43 BI H3 SHEET 3 OF 3 an x KAM PID 10 4583 00 P A Pmam BOARD wow 555 488 INTER 7A C GHVOS lOOLd VId ...

Page 57: ...ativewill contactyou concerning any change in part number Change information if any is located at the rear of this manual SPECIAL NOTES AND SYMBOLS X000 Part first added at this serial number 00X Part removed after this serial number ITEM NAME In the Parts List an Item Name is separated from the description by a colon 2 Because of space limitations an Item Name may sometimes appear as incomplete F...

Page 58: ...EMICONDUCTOR DR SANTA CLARA CA 95051 32159 WEST CAP ARIZONA 2201 E ELVIRA ROAD TUCSON AZ 85706 3h630 TYCO FILTERS DIV INC 3940 W MONTECITO PHOENIX AZ 85019 50434 HEWLETT PACKARD COMPANY 640 PAGE MILL ROAD PALO ALTO CA 94304 56289 SPRAGUE ELECTRIC CO 87 MARSHALL ST NORTH ADAMS MA 01247 59660 TUSONIX INC 2155 N FORBES BLVD TUCSON AZ 85705 72982 ERIE TECHNOLOGICAL PRODUCTS INC 644 W 12TH ST ERIE PA 1...

Page 59: ...FXD CER DI 0 IUF 80 ZOZ 50V 72982 8121N083ZSU01042 0115 283 0024 00 CAP FXD CER DI O 1UF 80 ZOZ 50V 72982 8121N083zsuo104z 0116 283 0024 00 CAP FXD CER DI 0 1UF 80 ZOZ 50V 72982 8121N083ZSU01042 0117 283 0024 00 CAP FXD CER DI 0 IUF 80 ZOZ 50V 72982 8121N08325U01042 c118 283 0024 00 CAP FXD CER DI O 1UF 80 ZOZ 50V 72982 8121N083zsuo104z 0119 283 0024 00 CAP FXD CER DI 0 IUF 80 20Z 50V 72982 8121N0...

Page 60: ... SZ O 25W 01121 081025 R42 315 0102 00 RESD FXD CMPSN 1K01m 5z 0 25w 01121 081025 800 315 0103 00 888 FXD CMPSN 10K OHM SZ 0 25W 01121 081035 8100 315 0910 00 RES FXD CMPSN 91 088 5z 0 25w 01121 089105 8120 315 0102 00 RES FX D CMPSN 1K 0181 5z 0 258 01121 081025 8121 315 0102 00 RES FXD CMPSN 1K 01m 5z 0 25w 01121 081025 8122 315 0102 00 RES FXD CMPSN 1K 01m 5z 0 2sw 01121 081025 8123 315 0302 00...

Page 61: ... STATIC PRGM 80009 160 0180 00 0114 160 0179 00 MICROCIRCUIT DI 1024 x 0 STATIC PRGM 80009 160 0179 00 0115 160 0178 00 MICROCIRCUIT DI 1024 x 3 STATIC PRGM 30009 160 0178 00 U116 156 0061 00 MICROCIRCUIT DI SGL BCD TO DEC DECODER 01295 SN7442 N OR J U117 156 0916 00 MICROCIRCUIT DI EIGHT 2 INP 3 STATE BFR 80009 156 0916 00 U118 156 0535 00 MICROCIRCUIT DI TRI STATE HEX BUFF 27014 DM8097M U119 156...

Page 62: ... 156 0383 00 11323 156 0480 OO mcaocmcuummmn 2 mpur AND am 01295 SNMLSOBW OR J U324 156 0849 00 MICROCIRCUIT DI QUADINTERFACE BUS XSVR 80009 156 0849 00 U325 156 0849 00 MICROCIRCUIT DI QUADINTERFACE BUS XSVR 80009 156 0849 00 11413 156 0041 00 uxcxocmcumnnnuu 11 11111 FLIP FLOP 27014 01174741 U414 156 0718 00 MICROCIRCUIT DI TRIPLE 3 INP PCS NOR GATES 80009 156 0718 00 U418 156 0323 00 mcaocmcuu ...

Page 63: ...PARTS Attaching Parts always appear in the same indentation as the item it mounts while the detail parts are indentedto the right lndented items are part of and included with the next higher indentation Attaching parts must be purchased separately unless otherwise specified ABBREVIATIONS INCH ELCTRN ELECTRON a NUMBER SIZE ELEC ELECTRICAL ACTR ACTUATOR ELCTLT ELECTROLVTIC ADPTR ADAPTER ELEM ELEMENT...

Page 64: ...O 77900 SHOKEPROOF OIV OF ILLINOIS TOOL WORKS 70189 ILLINOIS TOOL NORKS INC SHAKEPRODF DIVISION 00009 TEXTRONIX INC 93907 TEXTRON INC CONCOR OIV TK0435 LENIS SCREN CO 6 8 1 COMPONENT PORK 60 RUOUBON R0 446 BLAKE ST 7100 LﬂHPSON AVE RICHARDS OVE 30 HUNTER LONE 33 E FRONKLIN ST SOINT CHARLES R0 ST CHARLES R000 4900 S H GRIFFITH OR P 0 BOX 500 600 18TH OVE 4114 S PEORIO NEST BRIOGENOTER MO 02379 NAKE...

Page 65: ...4P 108T 22 136 0514 00 2 SKT PL IN ELEK NICROCIRCUIT 8 DIP 09922 DILBBP 108 23 136 0252 07 3 SDCKET PIN CONN N 0 DINPLE 22526 75060 012 24 214 0579 00 5 TERN TEST POINT BRS CD PL 80009 214 0579 00 25 1 NICRDCIRCUIT SEE U312 REPL ATTACHING PARTS 26 210 0586 00 NUT PL ASSEN NAz4 4O X 0 25 STL CO PL 78189 211 041800 00 27 211 0097 00 SCREN NACHINE 4 40 X 0 312 PNH STL TXD435 ORDER BY DESCR END ATTACH...

Page 66: ...a lAssembly No Mfr No Part No Effective Dscont Qty 12345 Name 8 Description Code Mfr Part No 1 012 0530 01 8010100 8100795 1 C118LE INTCON 2 0H L 04919 2024 2 OPTION 31 ONLY 012 0630 03 8100796 1 CABLE INTCON 2 0I L 74868 DC30147 102 OPTION 31 ONLY 6 1 0 REV DEC 1986 ...

Page 67: ...IQ mxvroumo 021 0206 00 ...

Page 68: ...le Length 0 Seven Addressing Modes Direct Relative Immediate Indexed Extended Implied and Accumulator 0 Variable Length Stack O Vectored Restart O Maskable Interrupt Vector 0 Separate Non Maskable Interrupt Internal Registers Saved In Stack 0 Six Internal Registers Two Accumulators Index Register Program Counter Stack Pointer and Condition Code Register L SUFHX 0 Direct Memory Addressing DMA and M...

Page 69: ...ow Voltage VOL VSS 0 4 Vdc Load 1 6 mAdc VCC min Power Dissipation PD 0 600 1 2 W Capacitance 1 192 Cin 80 120 160 pF Vin 0 TA 25 C f 1 O MHZ TSC 15 DBE 7 0 10 DO D7 10 12 5 Logic Inputs 6 5 8 5 A0 A15 R W VMA cout 12 pF Frequency of Operation f 0 1 1 0 MHz Clock Timing Figure 1 Cycle Time tcyc 1 0 10 us Clock Pulse Width PW H ns Measured at VCC 0 3 V 1 430 4500 1 2 450 4500 Total 1 1 and 212 Up T...

Page 70: ... ns Input Data Hold Time tH 10 ns Output Data Hold Time tH 10 25 ns Address Hold Time Address R W VMA tAH 50 75 ns Enable High Time for DBE Input tEH 450 ns Data Delay Time Write tDDW 165 225 ns Processor Contro s Processor Control Setup Time tpcs 200 ns Processor Control Rise and Fall Time tPCr tpcf 100 ns Bus Available Delay tBA 300 ns Three State Enable tTSE _ 40 ns Three State Delay tTSD 700 n...

Page 71: ...DELAY versus CAPACITIVE LOADING SOU IDH 40 pA max 2 4 V IOL 1 8 mA max 0 4V Vcc 530 V TA 22590 500 400 300 DELAY TIME n5 200 100 CL includes stray capacitance 200 300 400 CL LOAD CAPACITANCE pF 500 600 DELAY TIME ns FIGURE 5 TYPICAL READ WRITE VMA AND ADDRESS OUTPUT DELAY versus CAPACITIVE LOADING 600 IDH I45p A max 2 4 V IOL 1 5 mA max 0 4V VCC 5 0 V TA 25 C 500 400 Address V 300 200 100 CL inciu...

Page 72: ... 120 D L D U 5 100 0 20 4o 60 so 100 120 TA AMBIENT TEMPERATURE OC EXPANDED BLOCK DIAGRAM A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 25 24 23 22 2o 19 1B 17 1s 15 14 13 12 11 1o 9 Output Buffers Output Buffers Clock 1 3 Clock 02 37 Rese t 40 Program Counter Program Counter NonvMaskabIa Interrupt 6 H711 2 _ Instruction Decode and Control Interrupt Request 4 ThreeState Control 39 Data Bus...

Page 73: ...rd TTL load and 90 pF may be directly driven by this active high signal Data Bus Enable DBE This input is the three state control signal for the MPU data bus and will enable the bus drivers when in the high state This input is TTL com patible however in normal operation it would be driven by the phase two clock During an MPU read cycle the data bus drivers will be disabled internally When it is de...

Page 74: ... the cycle a 16 bit address will be loaded that points to a vectoring address which is located in memory locations FFFC and FFFD An address loaded at these locations causes the MPU to branch to a non masﬂﬂe interrupt routine in memory NMI has a high impedance pullup resistor internal to the chip however a 3 k9 external resistor to VCC should be used for wire OR and optimum control of interrupts In...

Page 75: ...egister that contains the address of the next available location in an external push down pop up stack This stack is normally a random access Read Write memory that may have any location address that is convenient In those applications that require storage of information in the stack when power is lost the stack must be non volatile Index Register The index register is a two byte register that is ...

Page 76: ... Carry From Bit 3 FIGURE 12 SAVING THE STATUS OF THE MICROPROCESSOR IN THE STACK SP Stack Pointer ACCB Accumulator B ACCA Accumulator A CC Condition Codes Also called the Processor Status Byte iXH Index Register Higher Order 8 Bits lXL 2 Index Register Lower Order 8 Bits PCH Program Counter Higher Order 8 Bits PCL Program Counter Lower Order 8 Bits m 2 m 1 m 1 m 2 i I Before m 9 m 8 m 7 m 6 m 5 m ...

Page 77: ...sing the address contained in the second byte of the instruction is added to the index register s lowest eight bits in the MPU The carry is then added to the higher order eight bits of the index register This result is then used to address memory The modified address is held in a temporary address regis ter so there is no change to the index register These are two byte instructions Implied Address...

Page 78: ...I R o ORAB CA 2 2 DA 3 2 EA 5 2 FA 4 3 B M B O O I I R O PushData PSHA 3G 4 I A Msp SP I SP O C O 0 0 0 PSHB 37 4 I B MSP SP I SP O 0 0 0 0 Pull Dara PULA 32 4 I SP 1ASP MSp A I o o o o o PULB 33 4 I SP IASP M3p B o o o o 0 o Rotate LeII ROL 59 7 2 79 6 3 M o o t I t ROLB 59 2 1 e C W b0 I t z Rotate Right ROR 56 7 2 7e 5 3 M o o I 1 RORA as 2 1 A EI_ TEEEEEEEE 3 I 2C RORB 56 2 1 B 0 b7 b0 t t t S...

Page 79: ...ranch Always BRA 20 4 2 None 0 o o o o 3 Branch If Carry Clear 800 24 4 2 C J o o o o o a Branch If Carry Set 808 25 4 2 C 1 0 a o o o a Branch II Zero BED 27 4 2 Z 1 0 o o o o a Branch If Zero BGE 2C 4 2 N V 0 o o o o o 0 Branch If Zero BGT 2E 4 2 Z N 9 V 0 o o o o o 0 Branch II Higher BHI 22 4 2 C Z 0 o 0 o o o 0 Branch If Zero BLE 2F 4 2 Z N 9 VI 1 0 o o o o 0 Branch If Lower Dr Same BLS 23 4 2...

Page 80: ...t Main Instr TABLE 6 CONDITION CODE REGISTER MANIPULATION INSTRUCTIONS COND CODE REG IMPLIED 5 4 3 Z 0 OPERATIONS MNEMONIC OF N BOOLEAN OPERATION H I N Z V C Clear Carry CLC 00 2 I 0 C O O O 0 I R Clear Interrupt Mask CLI GE 2 I 0 I O R O 0 o 0 Clear Overflow CLV 0A 2 I 0 V 0 0 0 0 R 0 Set Carry SEC 00 2 I I C O I O O O S Set Interrupt Mask SEI 0F 2 I I 9 0 S D 0 I 0 Set Overflow SEV 08 2 I I V o ...

Page 81: ...OUIODOIIOVVU IU IU IOIndexed oon I IICODAbmt bbbbabobbxxauaooootoRelative OAbONCOONINNNOOQIOOIO IIIUIIDOIIOODNImpIIed a no 0103 Interrupt time is 12 cycles from the end of the Instrucﬁon being executed except foltowing a WAI instruction Then It is 4 cycles Dual OperandI Ioon ucoon oust commoooommooocioomACCX coooco oomoooooomooooooom oowumoooanImmediate aon an 0 0mm uwooooooomooobbwoooooDirac 0bb ...

Page 82: ...ddress 1 Op Code t8 4 2 1 Op Code Address 1 1 Address of Operand 3 1 Address of Operand 1 Operand Data High Order Byte 4 1 Operand Address 1 1 Operand Data Low Order Byte STA 1 1 OpCodeAddmg 1 OpCode 4 2 1 Op Code Address 1 1 Destination Address 3 0 DestinationAddress 1 Irrelevant Data Note 1 4 1 DestinationAddress 0 Data from Accumulator STS 1 1 Op Code Address 1 Op Code STX 2 1 Op Code Address 1...

Page 83: ...ter 1 Irrelevant Data Note 1 8 4 1 Stack Pointer 0 Return Address Low Order Byte 5 1 Stack Pointer 1 0 Return Address High Order Byte 6 0 Stack Pointer 2 1 Irrelevant Data Note I 7 0 Index Register 1 Irrelevant Data Note 1 8 0 Index Register Plus Offset w o Carry 1 Irrelevant Data Note 1 EXTENDED JMP 1 1 Op Code Address 1 Op Code 3 2 1 Op Code Address 1 1 Jump Address High Order Byte 3 1 Op Code A...

Page 84: ...ruction CBA LSR TAB CLC NEG TAP CLI NOP TBA CLR ROL TPA CLV ROR TST COM SBA DES 1 1 Op Code Address 1 Op Code PNESX 4 2 1 Op Code Address 1 1 Op Code of Next Instruction INX 3 0 Previous Register Contents 1 Irrelevant Data Note 1 4 0 New Register Contents 1 Irrelevant Data Note 1 PSH 1 1 Op Code Address 1 Op Code 4 2 1 Op Code Address 1 1 Op Code of Next Instruction 3 1 Stack Pointer 0 Accumulator...

Page 85: ... 0 Index Register Low Order Byte 12 6 1 Stack Pointer 3 0 Index Register High Order Byte 7 1 Stack Pointer 4 0 Contents of AccumulatorA 8 1 Stack Pointer 5 0 Contents of AccumulatorB 9 1 Stack Pointer 6 0 Contents of Cond Code Register 10 0 Stack Pointer 7 1 Irrelevant Data Note 1 11 1 Vector Address FFFA Hex 1 Address of Subroutine High Order Byte 12 1 Vector Address FFFB Hex 1 Address of Subrout...

Page 86: ...ration of the interface 8 Bit Bidirectional Data Bus for Communication with the MPU Two Bidirectional 8 Bit Buses for Interface to Peripherals Two ProgrammableControl Registers Two ProgrammableData Direction Registers Four Individually Controlled Interrupt Input Lines Two Usable as Peripheral Control Outputs 0 HandshakeControl Logic for Input and Output Peripheral Operation L SUFFIX O High Impedan...

Page 87: ...1 0 MHz 00 07 12 5 __ PAO PA7 PBO PB_7 CA2 C82 10 R W Reset R80 R81 CSO CS1 CS2 CA1 CB1 7 5 Output Capacitance WERTQB Com 5 0 pF Vin 0 TA 25 C f 1 0 MHz PBO PB7 10 Peripheral Data Setup Time Figure 1 tPDSU 200 e ns Delay Time Enable negative transition to CA2 negative transition tCA2 1 0 us Figure 2 3 Delay Time Enable negative transition to CA2 positive transition TRSl 1 0 us Figure 2 Rise and Fa...

Page 88: ... Address and R W valid to Enable positive transition tAS 160 ns Data Delay Time tDDR 320 ns Data Hold Time tH 1O ns Address Hold Time tAH 10 ns Rise and Fall Time for Enable input tEr tEf 25 ns WRITE Figures 11 and 12 Enable Cycle Time tcch 1 0 3 Enable Pulse Width High PWEH 0 45 25 us Enable Pulse Width Low PWEL 0 43 us Setup Time Address and R W valid to Enable positive transition tAS 160 ns Dat...

Page 89: ...pulse Enable 2 4 V r i l twtf 7 1 C81 2 0 V X 5 0 8 v r 7 tcez tnsz a 2 4 v 82 C 0 4 V Assumes part was deselected during any previous E pulse FIGURE 8 IRO RELEASE TIME FIGURE 9 RESET LOW TIME 2 4 V lR 2 4 V tRL Reset E 0 8 V g The Reset line must be a VlH for a minimum of 1 0 is before addressing the PIA FIGURE 10 BUS READ TIMING CHARACTERISTICS Read Informationfrom PIA FIGURE 11 BUS WRITE TIMING...

Page 90: ...output buffers are enabled when the proper address and the enable pulse E are present m The active low Re set line is used to reset all register bits in the PIA to a logical zero low This line can be used asa power on reset and as a master reset during system operation PIA Chip Select C80 C81 and 63 2 These three input signals are used to select the PIA C50 and C81 must be high and m must be low f...

Page 91: ... 4 PA2 Peripheral H5 PA3 InterAface 6 FAA H 7 PAS Bus nput m Register 5 8 PAS BIR E51 H9 PA V P 20 cc l 1o PBO VSS Pin 1 Output H11 P81 Register 8 ORB 12 P82 cso 22 Peripheral H13 P83 Interface CS1 24 B 14 P84 C82 23 Chip H15 P85 Select R50 36 and H16 P136 RS1 35 R W H17 PB7 R W 21 I Control Enable 25 A Reset 34 Data Direction Control Register B Register a DDR8 CRB 18 CB1 interrupt Status IRQB 37 ...

Page 92: ...ansferred into the MPU on a Read operation to differ from that contained in the respective bit of Output Register A Section B Peripheral Data PBO PB7 The peripheral data lines in the B Section of the PIA can be programmed to act as either inputs or outputs in a similar manner to PAO PA7 However the output buffers driving these lines differ from those driving lines PAO PA7 They have three state cap...

Page 93: ...he two registers are read only and are modified by external interrupts occurring on control lines CA1 CA2 CBI or C82 The format of the control words is shown in Table 2 TABLE 2 CONTROL WORD FORMAT 7 6 5 I 4 I 3 2 1 I 0 CRA IROAI IROA2 CA2 Control DDRA CA1 Control Access 7 6 5 I 4 I 3 2 1 I 0 CR8 IRQBI IROBZ CB2 Control DDRB CB1 Control Access Data Direction Access Control Bit CRA 2and CR B 2 Bit 2...

Page 94: ...ndicates negative transition high to low 3 The Interrupt flag bit ORA 6 is cleared by an MPU Readof the A DataRegisterand ORB 6 is cleared by an MPU Read of the B Data Register 4 If ORA 3 ORB 3 is low when an interrupt occurs Interrupt disabled and is later brought high IROA IRQB occurs after CRA 3 CRB 3 is written to a one TABLE 5 CONTROL OF CBZ AS AN OUTPUT ORB 5 is high CB2 ORB 5 ORB 4 CRB a Cl...

Page 95: ...gh on an MPU Control Register A Write to Control Register A that changes ORA 3 to one 1 1 1 Always high as long as ORA 3 High when ORA 3 goes high as is high Will be cleared on an a result of an MPU Write to MPU Write to Control Register Control Register A A that clears CRA S to a zero PIN ASSIGNMENT PACKAGE DlMENSlONS CASE 715 02 CERAMIC 1EV CA1 J 40 SEE PAGE 165 FOR 2 E P23 CA2 1 39 PLASTIC PACK...

Page 96: ... CASE 709 O TTL Compatible 0 Maximum Access Time 350 ns MCM6810AL1 P 450 ns MCM6810AL ASS GNMENT 1 Gndo VCC2 24 2 I D0 A0 I 23 3 I Dl A1 I 22 ABSOLUTE MAXIMUM RATINGS See Note 1 4 l 02 A2 1 21 Rating Symbol Value Unit 5 I 03 A3 20 Supply Voltage VCC 0 3 to 7 0 Vdc 6 I 04 A4 1 19 Input Voltage Vin 0 3 to 7 0 Vdc 7 E 05 A5 I 18 Operating Temperature Range TA 0 to 70 0C 8 I 06 A6 17 9 07 Storage Temp...

Page 97: ...Supply Current ICC mAdc VCC 5 25 V all other pins grounded TA 0 C MCM681OAL 7O MCM6810AL1 c 80 CAPACITANCE f 1 0 MHz TA 25 C periodically sampled rather than 100 tested This device contains circuitry to protect the inputs against damage due to high static voltages Characteristic Symbol Max Unit or electrlc fields however It 15 advrsed that normal precautionsbe taken to avord applicatlon Input Capa...

Page 98: ...x Min Max Unit Read Cycle Time tcvciFi 450 350 ns Access Time tacc 450 350 ns Address Setup Time tAS 20 20 ns Address Hold Time tAH 0 0 ns Data Delay Time Read tDDR 230 180 ns Read to Select Delay Time tRCS 0 O ns Data Hold from Address tDHA 10 10 ns Output Hold Time tH 10 10 ns Data Hold from Write tDHW 10 80 10 60 ns READ CYCLE TIMING A t y FI I tacc i 2 0V dd A ress c0 8V tAS tAH a CS 2 0 v 0 8...

Page 99: ... 55 can be enabled for consecutlve write cycles provided R W is strobed to VIH before or coincident with the Address change and remains high for time AS Y _ See Page 165 for Plastic Package dimensions 0 25mm 0 010 DIA AT SEATING PLANE AT MAXIMUM MATERIAL g 7 CONDITION SEATING PLANE G _ I LEADSTRUE POSITIONEO WITHIN MILLIMETERS INCHES DIM MIN MAX MIN MAX A 29 97 30 99 1 180 1 220 B 14 88 15 82 0 58...

Page 100: ...IB Interface is set to 7 NOTE When operating in the optional mode the Single Sweep Reset SSR command and all of the DPO Front Panel PROGRAM CALL buttons should not be used The general format of the commands will be wrt 7Ql cmdA or wrt 791 cmd where the 7 of 7Q1 refers to the card setting on the 98034A HP IB Inter face the m1 refers to the primary address set on the DPO IEEE 488 Inter face DIP swit...

Page 101: ...ough 4 do the actual transfer WRITING DATA TO THE DPO To transfer data from the 9825 to the DPO use the following example as guide remember that the data must be integers in the range D to 1Q23 I dim A SLE 192 EB fmt L x f Z z El wtb 7Z1 DPX 22 for I l to 513 EB wrt 7Z1 L A I EH next I 25 wrt 7Z1 In the preceding example lines D through 19 dimension and define the con tents of variable A Line 2 is...

Page 102: ... this manual WRITING MESSAGES TO THE DPO The following example may be used to write messages or scale factors to the DPO U wrt 7ZL ADR 3455 L th 7Z1 SCL THIS IS LOTS OF FUN E wrt Z J3 ADR 7295 Lines 2 3 are not necessary to write 3 wrt 7uL OCT ZHELDZ into Field ﬂ addresses 2p48 2559 H end In the foregoing example line D sets up the DPO address register to Field 2 waveform D Line 1 transfers the me...

Page 103: ... entry to the above routine the variable A should be set to the value of the primary address of the DPO On exit the status byte will be displayed on the 9825 in decimal This routine could be made a subroutine by modify ing line 36 by replacing the dsp rZ with ret which would leave the dec imal status byte in r2 then return to the calling routine The following detailed description will be useful to...

Page 104: ... be made again the 7 corresponds to the selector switch set ting wti 6 77 places UNL UNListen on the IEEE 488 lines ATN is assert ed wti 6 r2 tells the controller to listen wti 6 36 issues the command SPE Serial Poll Enable wti 6 r3 tells the UPC to talk rdi 4 r2 triggers the interface to read and rdi 4 r2 reads the data and places status byte into r2 In line 35 wti 6 137 performs UNT UNTalk wti 6...

Page 105: ......

Page 106: ... 37 35 53 45 69 55 85 65 101 75 117 0 11 ACK SYN 6 F V f v 6 6 16 22 26 38 36 54 46 70 56 86 66 102 76 118 12 1 1 1 BEL ETB 7 G W w 7 7 17 23 27 39 37 55 47 71 57 87 67 103 77 119 1 0 1a 11 BS CAN 8 H X h x 8 8 18 24 28 40 38 56 48 72 53 88 68 104 78 120 1 mw1 H EM 9 I Y 1 y 9 9 19 25 29 41 39 57 49 73 59 89 69 105 79 121 1m1 LF SUB Z A 10 1A 26 2A 42 3A 58 4A 122 74 5A 90 6A 106 7A k 75 SB 91 6B ...

Page 107: ......

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