Tektronix CSA 803C, Service Manual

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3Ć23
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This coprocessor is a highĆspeed, floatingĆpoint processor that executes
instructions in parallel with the EXP. The EXP programs and controls the
numeric coprocessor as an I/O device at addresses 0F8 to 0FF .
!
This circuit consists of a data buffer, an address buffer, and a control buffer
that provide command and control signals from the microprocessor to the
three Executive busses. The Executive busses consist of the following:
# ! Ċ is a bidirectional bus. It allows the microproĆ
cessor to fetch instructions from memory, and also to write data to
memory and read data from memory. The memory that the microprocesĆ
sor uses is located on the A18 Memory board.
# ! Ċ carries the address of a device when the
microprocessor is requesting access to that device. Once the microproĆ
cessor has access, the addressed device can then respond to the
microprocessor.
# ! Ċ carries control signals sent by the microproĆ
cessor. These control signals are sent to the devices that the microproĆ
cessor addresses, so that the devices can respond at the proper
moment in the bus cycle.
This circuit generates synchronized ready and reset control signals.
This circuit extends the bus cycle with wait states so that slower devices
have sufficient time to read or write data.
!
These circuits constantly monitor the EXP's interrupt lines to ensure that the
highest priority interrupt gets serviced first. The Interrupt controllers provide
the ability to assign priority levels to all the system's interrupt lines and,
conversely, to ignore (mask) any of the interrupt lines as well.
This circuit shortens the GPIB transfer time as well as the transmission time
of waveforms through the GPIB.