Page Register
7
6
5 4 3 2 1 0
RSVD RSVD
PAGE_SELECT
Address
:
Base + 4 (Read/Write)
Definition:
This register allows one to select the current page when in paged mode.
At reset PAGE_SELECT is set to 0x00.
Bit Description:
PAGE_SELECT:
When in paged mode this register allows one to select
one of 64 pages for NVRAM access (each page is 32
KB). This allows up to 2 MB of NVRAM.
RSVD
:
Reserved.
Mode Register
7
6
5 4
3
2
1
0
LINEAR PAGED TEST_MODE
RSVD DECODE
MEM_SELECT
Address:
Base + 5 (Read/Write)
Definition:
This register provides various system configuration options. This
register defaults to zero indicating NVRAM doesn’t appear anywhere
in memory space after power up or a system reset.
Note:
When the LINEAR bit is set PAGED and MEM_SELECT bits
1 through 3 are ignored.
Bit Description:
LINEAR
:
When this bit is set NVRAM appears as linear
memory. This mode is not compatible with x86-
based systems.
PAGED
:
When this bit is set NVRAM appears in a 32 KB
window. One can use the PAGE_SELECT register to
select the current page. This bit must be set on x86-
based systems.
TEST_MODE:
This bit is used for factory testing to change between
8 and 16 bit mode.
DECODE
:
When this bit is clear only address lines 15 through
19 are used for decoding (recommended for x86
platforms). When this bit is set address lines 15
though 21 are used for decoding (recommended for
TS-ARM based platforms).
MEM_SELECT
: When in paged mode this register can be used to
select the base address. If the DECODE bit is set,
base addresses are as follows.
8
Summary of Contents for TS-NVRAM2
Page 1: ...TS NVRAM2 Manual i...
