TS-7250 MANUAL
COMMON INTERFACES GENERAL INFORMATION
4 COMMON INTERFACES GENERAL INFORMATION
The purpose of this section is to provide general information about the common
interfaces, such as Serial Ports and Digital Input/Output, which appear in more than one
header or connector of the
TS-7250
. For further information on these features, refer to the
Connectors and Headers section of this manual.
4.1 Serial Ports
The
TS-7250
have two asynchronous serial ports (COM1 and COM2) which provide a
means to communicate with external serial devices. Each is independently configured as
a 16C550- type COM port that is functionally similar to a standard PC COM port. These
ports have 16-byte FIFOs in both the receive and the transmit UART channels. Both COM
ports can support all standard baud rates up through 230.4Kbaud. Both COM ports may
be configured to use a DMA channel (useful when very high baud rates are being used).
COM1 and COM2 UARTs can generate:
✔
Four individually maskable interrupts from the receive, transmit, and modem status
logic blocks
✔
A single, combined interrupt that is asserted if any of the individual interrupts are
asserted and unmasked
The COM1 port can also support the HDLC protocol. Refer to the Cirrus EP9301 User's
Guide for more details. The COM2 port can optionally support RS-485 half or full duplex
levels.
4.2 Digital I/O
There are 20 Digital Input/Output (DIO) lines available on the
TS-7250
. These are
available on two headers labeled “DIO” and “LCD”. The header labeled LCD can be used
as 11 DIO lines or as an alphanumeric LCD interface. The header labeled DIO has 9 DIO
pins available. In addition to the DIO signals, each header also has a power pin and
Ground available. The LCD header has 5V power available while the DIO header has
3.3V power.
The DIO2 header (FPGA DIO) is controlled by the on-board FPGA. It is a 40-pin header
divided in two sub-headers of 20 pins each. On the first header, by default, there are 17
video signals that can be changed into digital I/O, while the second, labeled DIO2, has 18
digital I/O lines which implement two XDIO ports. Thus, there are 35 total DIO lines
connected directly to the on-board FPGA on the
TS-7250
available through the 40-pin
header. The first header has 5V power available and the second (DIO2) has 3.3V power.
Three pins on the DIO header are used to bring out the EP9302 SPI bus. By using some
of the DIO pins as peripheral Chip Select signals, a complete interface is available for SPI
peripherals. It is also possible to bring out a fourth SPI bus function [SPI_Frame] by
adding a 10 ohm resistor in the position labeled R1 on
TS-7250
boards. This signal is not
required for many SPI peripherals but it may prove useful in some applications.
All of the DIO lines are programmable as either inputs or outputs and the direction of each
I/O pin can be individually programmed. All DIO control registers are 8-bits wide and
aligned on word (32-bit) boundaries. For all registers, the upper 24 bits are not modified
when written and are always read back as zeros. Every DIO pin has two registers used to
access it, an 8-bit data register and an 8-bit data direction register (DDR). The DDR
controls whether each DIO pin is an input or an output (”1” = output). Writing to the data
register only affects pins that are configured as outputs. Reading the data register always
returns the state of the DIO pin.
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