Teac MV1421, Service Manual

Page: 17 / 130

15
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Synchronization
d is p la y s yn c h ro n iza tio n to s a n d ca s tle o r h o riz o n ta l sy n c a n d ve rtic a l sy n c w ith s ta rt/sto p o s c illa to r o r d is p la y
synchroniza tion to H S /V S w ith exte rnal clock independent clock syste m s for acquisition, displa y and contro ller.
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Controller
- 8 b it c o n fig u ra tio n
- 1 8 in tern a l clo c k
- 0 .3 3 ins tru c tio n cy c le
- e igh t 1 6 b it d a ta p o in te r re g is te rs (D PT R )
- tw o 1 6 b it tim e rs
- w a tch d o g tim e r
- s e ria l inte rfa c e (U A R T )
- 1 K b yte o n ch ip e xte n d ed R A M (a cc e ss via M O V X )
- 8 K b yte o n ch ip A C Q bu ffe r R A M (a cc e ss v ia M O V X )
- 6 c h a n n e l 8 b it P W M u n it
- 2 c h a n n e l 1 4 b it P W M u n it
- 4 m u ltip le x e d A D C in p u ts w ith 8 b it re so lutio n
- o n e 8 b it I/O p o rt w ith o p e n d ra in o u tp u t a n d o p tio n al IIC e m ula tio n
- tw o 8 b it m u ltifun c tio n al I/O p o rts
- o n e 4 b it p o rt w o rkin g a s d ig ita l o r a n a lo g in p u ts
- o n e 2 b it I/O p o rt w ith o p tio n a l a d d re ss la tc h e n a b le fu n ctio n
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P-SDIP 52 package
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5V supply voltage
3. BLOCK DIAGRAM
WATCHDOG
ADC
PWM
TTX
VPS
SLICER
ACK
DISPLAY
TIMING
CHAR.ROM
448*12*10
DISPLAY
GEN.
C500
CPU
ROM
32KB
EXTENDED
RAM
1KBYTE
DUAL PORT
INTERFACE
VBI BUFFER
1KB
DUAL PORT
INTERFACE
DISPLAY
PAGE 8KB