17.
AK33 CHASSIS MANUAL ADJUSTMENTS PROCEDURE ___________26
1.
INTRODUCTION
11AK33 is a
110ø chassis capable of driving 28-29”,32”,33” tubes at appropriate currents
The chassis is
a
Frequency Controlled Tuning (PLL) and control system for multi-standard TV receivers with on-
screen-display (OSD) for all relevant control functions. The system is based on the ‘one-chip’ I
2
C bus
controlled video processing / deflection IC TDA8885 which also controls sound.
German stereo and Nicam is detected and processed by the MSP 3410 G. Dolby sound is processed by
MSP 3452 G, virtual dolby by MSP 3411G, BTSC Stereo by MSP 3430G IC’s by option. All sound
processors also control the sound volume, balance, tone and spatial stereo effect.
The user-interface is menu based control system with cursor keys. Only for some functions the colour
keys are needed: This means that some of the functions can also be operated from the local keyboard
(i.e. Vol -, Vol +, P -, P+ and M).
Teletext is done by the microcontroller on-chip teletext module.
2.
SMALL SIGNAL PART WITH TDA8885
The TDA8885 combine all small signal functions required for a colour TV receiver.
2.1.
Vision IF amplifier
The IF-amplifier contains 3 ac-coupled control stages with a total gain control range, which is higher
then 66 dB. The sensitivity of the circuit is comparable. The video signal is demodulated by means of
an alignment-free PLL carrier regenerator with an internal VCO. This VCO is calibrated by means of a
digital control circuit, which uses the clock frequency of the m-Controller/Teletext decoder as a
reference. The frequency setting for the various standards (33.4, 33.9, 38, 38.9, 45.75 and 58.75 MHz)
is realised via the I 2 C-bus. To get a good performance for phase modulated carrier signals the control
speed of the PLL can be increased by means of the FFI bit. The AFC output is generated by the digital
control circuit of the IF-PLL demodulator and can be read via the I 2 C bus. For fast search tuning
systems the window of the AFC can be increased with a factor 3. The setting is realised with the AFW
bit. The AGC-detector operates on top sync and top white-level. The demodulation polarity is switched
via the I 2 C-bus. The AGC detector capacitor is integrated. The time-constant can be chosen via the I 2
C-bus. The time-constant of the AGC system during positive modulation is rather long to avoid visible
variations of the signal amplitude. To improve the speed of the AGC system a circuit has been included
which detects whether the AGC detector is activated every frame period. When during 3 field periods
no action is detected the speed of the system is increased. For signals without peak white information
