Teac 17MB10, Service Manual

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41
22” TFT TV Service Manual 13/10/2004
12.8. 24C32
12.8.1. General Description
The AT24C32/64 provides 32,768/65,536 bits of serial electrically erasable and programmable read only
memory (EEPROM) organized as 4096/8192 words of 8 bits each. The device’s cascadable feature allows
up to 8 devices to share a common 2-wire bus. The device is optimized for use in many industrial and
commercial applications where low power and low voltage operation are essential. The AT24C32/64 is
available in space saving 8-pin JEDEC PDIP, 8-pin JEDEC SOIC, 8-pin EIAJ SOIC, and 8-pin TSSOP
(AT24C64) packages and is accessed via a 2-wire serial interface. In addition, the entire family is available
in 2.7V (2.7V to 5.5V) and 1.8V (1.8V to 5.5V) versions
.
12.8.2. Features
•
Low-Voltage and Standard-Voltage Operation
•
Low-Power Devices (I
SB
= 2 µA at 5.5V) Available
•
Internally Organized 4096 x 8, 8192 x 8
•
2-Wire Serial Interface
•
Schmitt Trigger, Filtered Inputs for Noise Suppression
•
Bidirectional Data Transfer Protocol
•
100 kHz (1.8V, 2.5V, 2.7V) and 400 kHz (5V) Clock Rate
•
Write Protect Pin for Hardware Data Protection
•
32-Byte Page Write Mode (Partial Page Writes Allowed)
•
Self-Timed Write Cycle (10 ms max)
•
High Reliability
•
Automotive Grade and Extended Temperature Devices Available
•
8-Pin JEDEC PDIP, 8-Pin JEDEC SOIC, 8-Pin EIAJ SOIC, and 8-pin TSSOP Packages
12.8.3. Pin Description
SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each EEPROM device and
negative edge clock data out of each device.
SERIAL DATA (SDA): The SDA pin is bidirectional for serial data transfer. This pin is open-drain driven
and may be wire-ORed with any number of other open-drain or open collector devices.
DEVICE/PAGE ADDRESSES (A2, A1, A0): The A2, A1 and A0 pins are device address inputs that are
hard wired or left not connected for hardware compatibility with AT24C16. When the pins are hardwired, as
many as eight 32K/64K devices may be addressed on a single bus system (device addressing is
discussed in detail under the Device Addressing section). When the pins are not hardwired, the default A
2
,
A
1
, and A
0
are zero.
WRITE PROTECT (WP): The write protect input, when tied to GND, allows normal write operations. When
WP is tied high to V
CC
, all write operations to the upper quadrant (8/16K bits) of memory are inhibited. If left
unconnected, WP is internally pulled down to GND.