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[Table of Camera Link bit assignment] (showing correspondence relation between before and after encoding)
Camera Link port
(Node name)
Camera signal
name
I/O
Remark
Strobe
CLK
O
Pixel clock
LVAL
LDV
O
Horizontal synchronous timing
FVAL
FDV
O
Vertical synchronous timing
DVAL
-
O
(Fixed to H level)
Spare
-
O
(Fixed to H level)
8
BI
T
O
U
T
PU
T
PORTA0 / PORTB0
D00
O
Lowermost data
PORTA1 / PORTB1
D01
O
PORTA2 / PORTB2
D02
O
PORTA3 / PORTB3
D03
O
PORTA4 / PORTB4
D04
O
PORTA5 / PORTB5
D05
O
PORTA6 / PORTB6
D06
O
PORTA7 / PORTB7
D07
O
Uppermost data
PORTC0,1,2,3,4,5,6,7
O
(Fixed to L level)
1
0
BI
T
O
U
T
PU
T
PORTA0 / PORTC0
D00
O
Lowermost data
PORTA1 / PORTC1
D01
O
PORTA2 / PORTC2
D02
O
(Lowermost data at 8 bit scale)
PORTA3 / PORTC3
D03
O
PORTA4 / PORTC4
D04
O
PORTA5 / PORTC5
D05
O
PORTA6 / PORTC6
D06
O
PORTA7 / PORTC7
D07
O
PORTB0 / PORTB4
D08
O
PORTB1 / PORTB5
D09
O
Uppermost data
PORTB2,3,6,7
O
(Fixed to L level)
CC1
Vinit2
I
Asynchronous shutter trigger
CC2
(reserved)
I
(Reserved for future products)
CC3
(reserved)
I
(Reserved for future products)
CC4
(reserved)
I
(Reserved for future products)
SerTFG
TXD
O
URAT transmission data (Same timing as conventional RS-232C)
SerTC
RXD
I
URAT reception data (Same timing as conventional RS-232C)
* The port assignment is in conformity to “Base Configuration”, the standard of Camera Link.
External view of Camera Link cable assembly
(Note) The pin assignment is different between the PoCL Camera Link cable and the normal Camera Link cable.
Be sure to connect the cable after confirming that the cable is in conformity to PoCL. Note that the failure
associated with power activation of out-of-specification pins shall be exempt from charge-free repair.
Fi xing sc rew × 2
Twin -Ax c abl e
MD R-26 Twin -Ax cabl e ha rne ss (ma le)
MD R-2 6 Tw in -Ax ca bl e harness (mal e)
Fi xin g screw × 2
