Choose 4, 8, 16, 32, 64, 128, 256MB. Memory-mapped, graphics data structures can reside in the Graphics
Aperture.
3.4.13 Graphic Window WR Combin
Use this item to enable or disable data combination from buffer then write to memory feature.
3.4.14 Concurrent function (MEM) & (PCI)
Use these items to enable or disable concurrent memory/PCI and CPU action.
3.4.15 PCI Delayed Transaction
If the chipset has an embedded 32-bit write buffer to support delay transaction cycles, you can enable this
item to provide compliance with PCI Ver. 2.1 specifications. We recommend that you leave this item at the
default value.
3.4.16 Memory Parity Check
This item enables a parity check during boot-up memory testing. Only set this item to enabled if you are
using DRAM memory with parity.
3.5 Integrated Peripherals
You can control Input and Output functions from this screen.
Figure 3-5
Integrated Peripherals
CMOS Setup Utility - Copyright ( C ) 1984 - 2000 Award Software
Integrated Peripherals
> SIS 630 OnChip IDE Device
Press Enter
Item Help
> SIS 630 OnChip PCI Device
Press Enter
Menu Level >
> SIS 950 SuperIO Device
Press Enter
USB Controller
Enabled
USB Keyboard Support
Disabled
IDE HDD Block Mode
Enabled
Init Display First
PCI Slot
System Share Memory Size
8 MB
¯
®
¬
: Move Enter : Select +/-/PU/PD : Value F10 : Save ESC : Exit F1 : General Help
F5 : Previous Value F6 : Fail-Safe Defaults F7 : Optimized Defaults
3.5.1 SIS 630 OnChip IDE Device
CMOS Setup Utility - Copyright ( C ) 1984 - 2000 Award Software
SIS 630 OnChip IDE Device
Internal PCI/IDE
Both
Item Help
IDE Primary Master PIO
Auto
Menu Level >
IDE Primary Slave PIO
Auto
IDE Secondary Master PIO
Auto
IDE Secondary Slave PIO
Auto
IDE Primary Master UDMA
Auto
IDE Primary Slave UDMA
Auto
IDE Secondary Master UDMA
Auto
IDE Secondary Slave UDMA
Auto
IDE Burst Mode
Enabled
