CHAPTER THREE
3-8
bc620/627AT Time and Frequency Processor
Symmetricom, Inc.
STREN
Enables/disables the time coincidence strobe output. When disabled, the strobe output is always
low.
STRMODE
Selects the mode of operation for the time coincidence strobe. “Major/Minor” mode generates
an output pulse when both the major time (hours - seconds) and the minor time (milliseconds)
match the programmed strobe time (STROBE2 - STROBE6). “Minor Only” mode generates an
output pulse when the minor time matches the programmed strobe time (i.e. once per second).
FREQSEL0,1
Selects one of three clock output frequencies. The output frequency is either 1, 5, or 10 MHz.
3.1.4 EVENT0 - EVENT8 TIME CAPTURE REGISTERS (PAGE 1)
The EVENT0 - EVENT8 registers hold time which has been captured in response to the active
edge of the external event input the programmable periodic output, or a bus time request
accomplished by writing to the UNLOCK register. Time is captured only when the capture
sources (i.e. external event or periodic) are enabled with Bits 1 and 3 of CR0. This set of time
capture registers is completely separate from the TIME0 - TIME7 registers on page 0. Time is
captured to a resolution of 100 nanoseconds. The time capture lockout feature prevents the
EVENT0 - EVENT8 registers from being overwritten with a new time before they can be read
(See Section 3.2.3.3). Table 3-3 shows the time data format for these registers.
3.1.5 UNLOCK REGISTER (PAGE 1)
To release the time capture lockout mechanism, the UNLOCK register is read. The data read
from UNLOCK is undefined.
A write to the UNLOCK register latches time in the EVENT0 - EVENT8 registers. The data
written to the UNLOCK register is insignificant. This feature allows two independent times to
be captured via the PCbus by the host CPU
3.1.6 ACK REGISTER (PAGE 1)
The ACK data acknowledge register provides a means for acknowledging a data transfer to/from
the TFP via the FIFO interface, provides a mechanism for clearing the output FIFO and provides
a 1pps flag bit. Table 3-5 summarizes the function of each bit in the ACK register.
FIFO RX (Bit 0)
The 620/627AT acknowledges receipt of a valid input FIFO data packet by setting this bit. The
user is responsible for clearing the bit before instructing the TFP to take action on the FIFO data.
(Refer to bit 7).
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