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SC-TDC-1000 S Series Manual
SC-TDC-1000 S Series Manual | Surface Concept GmbH
Different settings of “nByte” parameter in combination with different settings of the “TimeTag” parameter
results in a further differentiation of the TimeTag functionality as described below:
“nBytes“ = 4
“nBytes“ = 8
“TimeTag“ = 0
“nBytes“ = 8
“TimeTag“ > 0
;each detector event x, y, t has a length of 32bit. The sub-definition for the different
coordinates x, y and t is defined by the “DataFormat“ (e.g. “DataFormat“ = 2 ;x = 11bit,
y = 11bit, t = 10bit, see the software manual for further details).
;each detector event x, y, t has a length of 64bit. The sub-definition for the different
coordinates x, y and t is defined by the “DataFormat“ (e.g. “DataFormat“ = 2 ;x = 11bit,
y = 11bit, t = 42bit, see the software manual for further details).
;each detector event x, y, t has a length of 64bit. The first 32bit are used for the tag
counter. The second 32bit are sub-definition for the different coordinates x, y and t is
defined by the “DataFormat“.
In case that “TimeTag“ > 0, “nBytes“ is set to 8 automatically within the software and any
ini file settings are ignored.
4.2.8 Master Reset Input (sub-R E8 only)
The master reset input is treated as an additional sign signal within the TDC and is counted up in a software
counter within the dll.
In addition the master reset input is connected to the reset pin of the TDC chip. Each time a signal is
applied to the master reset input the corresponding software counter is counting up and the input and
output FIFOs of the TDC chip are cleared (all old TDC data are erased).
A LVTTL (low voltage TTL) signal on 50Ohms has to be applied to the “MASTER RESET IN“ (BNC socket) of
the TDC.
4.2.9 State Signal Input (sub-R E8 only)
The state signal has to be applied as a LVTTL (low voltage TTL) signal on 50Ohms to the “STATE IN“ (BNC
socket) of the TDC.
In addition, the value of the variable named “TimeTag” in the tdc_gpx3.ini file (depending on the software
version which is used) must be adapted for the state/sign signal to be registered by the TDC.
The state or sign signal input assumes values 0 or 1, depending on the given electronic level of the LVTTL
signal (low or high).
For the state/sign input to be functioning the following variables in the tdc_gpx3.ini must be used:
TimeTag = 3
TimeTag = 4
TimeTag = 5
;must be set for using the state/sign input in combination with the ADC functionality
and the master reset input. The tag counting is switched off and any signal to the “TAG
IN“ is ignored.
;corresponds to the setting of TimeTag = 3
;must be set for using the state/sign input. Hereby the state/sign input functions in
combination with the tag signal functioning as a timer, counting the internal 80MHz
clock signal of the FPGA. A signal on “TAG IN“ resets the timer to 0.
