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X8DTT/-F/-IBX/-IBXF/-IBQ/-IBQF User's Manual
JF1
LE4
SW1
J18
JWR2
JWR1
FA
N2
FAN1
FAN4
JP10
JWOL1
J19
JWD1
J1
19
JPL1
JPG1
JPEN1
JBT1
LEB1 LEB2
LE2
JBAT1
JNMI1
JSPK1
J_UID_OW
T-SGPIO0
I-SA
TA
5
I-SA
TA4
P1 DIMM3B
P2 DIMM1A
P1 DIMM3A
P2 DIMM1B
P1 DIMM2B
P2 DIMM2A
P1 DIMM2A
P2 DIMM2B
P1 DIMM1B
P2DIMM3A
P2DIMM3B
VGA
COM1
LAN2
LAN1
USB0/1
IPMI_LAN
PCI-E 2.0 GEN2 X16
CPU2
I-SA
TA
3
I-SA
TA1
IPMB
USB2/3
I-SA
TA
0
PWR I2C
CPU1
T-SGPIO1
P1 DIMM1A
FA
N3
Battery
X8DTT Series
BIOS
I-SA
TA
2
Intel
5520/5500
Intel
ICH-10R
Nuvoton
WPCM450
PHY
InfiniBand CTRL
LAN CTRL
InfiniBand
Connector
4-pin PWR
(North Bridge)
(South Bridge)
JTPM1
LE1
Rev. 2.0
JBMC1
JPB
A
B
C
A. Fan1
B. Fan2
C. Fan3
D. Fan4
E. TPM Heaher
D
Fan Headers
There are four chassis/system fan head-
ers (Fan1 to Fan4) on the motherboard.
All these 4-pin fans headers are backward
compatible with the traditional 3-pin fans.
However, fan speed control is available
for 4-pin fans only. The fan speeds are
controlled by Thermal Management via
Hardware Monitoring in the BIOS. (The
Default setting is Disabled.) See the table
on the right for pin defi nitions.
Fan Header
Pin Defi nitions
Pin# Defi nition
1
Ground
2
+12V
3
Tachometer
4
PWR Modulation
Trusted Platform Module Header
A Trusted Platform Module (TPM) header
is located on the motherboard to provide
TPM support to enhance data integrity
and system security. See the table on the
right for pin defi nitions.
Trusted Platform Module (TPM) Header
Pin Defi nitions
Pin# Defi nition Pin # Defi nition
1
LPC Clock
2
GND
3
LPC FRAME#
4
Key
5
LPC Reset#
6
+5V (X)
7
LAD3
8
LAD2
9
+3.3V
10
LAD1
11
LAD0
12
GND
13
SCL
14
SDAT
15
+3V_DUAL
16
SERIRQ (X)
17
GND
18
CLKRUN(X)
19
LPCPD# (X)
20
LDRQ#(X)
Notes
:
(X)=TPM does not use the signals.
SCL, SDAT are I
2
C bus clock and data.
E
