Chapter 1: Introduction
1-9
1-2 Chipset and Processor Features Overview
The Intel® X48 Express chipset, designed for use with an ntel® Xeon® 3000
sequence/Core™ 2 Extreme/Core™ 2 Quad/Core™ 2 Duo processor in the LGA
775 Land Array Package, is comprised of two primary components: the Memory
Controller Hub (North Bridge) and the I/O Controller Hub (South Bridge). The
X7SBT/X7SBT - 10G provides the performance and feature-set required for the
mainstream server market.
Memory Controller Hub (X48/North Bridge)
The function of the MCH is to manage the data fl ow between four interfaces: the
CPU interface, the DDR3 System Memory Interface, the PCI Express Interface,
and the Direct Media Interface (DMI). The MCH is optimized for the Intel® Xeon®
3000/3200 series processor in the LGA775 Land Grid Array package. Four DIMM
slots support non-ECC Unbuffered Dual/Single Channel DDR3 1600 MHz up to
4GB in 2 DIMMs or DDR3 1333/1066/800 MHz up to 8GB in 4 DIMMs
The Ninth Generation I/O Controller Hub (ICH9R/South
Bridge)
The I/O Controller ICH9R provides the data buffering and interface arbitration re-
quired for the system to operate effi ciently. It also provides the bandwidth needed
for the system to maintain its peak performance. The Direct Media Interface (DMI)
provides the connection between the MCH and the ICH9R. The ICH9R supports
one PCI-Express device, four Serial ATA ports and up to six USB 2.0 portsheaders.
In addition, the ICH9R offers the Intel Matrix Storage Technology which provides
various RAID options for data protection and rapid data access. It also supports
next generation of client management through the use of PROActive technology in
conjunction with Intel's next generation Gigabit Ethernet controllers.
The I/O Controller Hub provides the I/O subsystem with access to the rest of the
system. Functions and capabilities include
Advanced Confi guration and Power Interface
•
Intel
•
® I/O External Design Specifi cation (EDS)
Intel
•
® X48 (Memory Controller Hub) External Design Specifi cation (EDS)
Intel
•
® ICH9R (I/O Controller Hub 9) Thermal Design Guideline
Intel
•
® 82573 Platform LAN Connect (PLC) PCI Design
