2-28
X10DRG-Q Motherboard User’s Manual
S-SGPI
O
I-SGPIO
2
BAR CODE
X10DRG-Q
Rev.1.01
MAC CODE
FA
N3
FA
N4
FA
N6/CPU
2
FA
N5/CPU
1
FA
N1
FA
N2
FA
NA
FANB
FANC
FAND
JBT1
LED1
SP1
J2
3
JVR1
JP
AC
1
JVRM
2
JVRM
1
JWD1
JPME
2
JPG1
JPB1
JPL1
JI2C
2
JI2C
1
JTPM
1
JSD1
JSD2
JHD_AC
1
JSPDIF_IN1
JL
1
JITP
1
JPI2C1
JTBT
1
BIOS
LICENSE
S-SA
TA
0
S-SA
TA
1
I-SA
TA
4
I-SA
TA
5
S-SA
TA
3
S-SA
TA
2
I-SA
TA
1
I-SA
TA
2
I-S
AT
A3
I-SA
TA
0
IPMI CODE
JIPMB1
AUDIO_FP
COM1
JBAT1
JPWR
4
JPWR
2
FA
N-I1
COM2
SUPERDO
M
USB 6 (3.0)
P1-DIMMC
1
P1-DIMMC
2
AL
WA
YS POPULA
TE DIMMx1 FIRST
CPU1
P1-DIMMD
2
P2-DIMME
1
P2-DIMMF
1
P2-DIMME
2
P2-DIMMF
2
LAN2
CPU2
P1-DIMMB
2
P1-DIMMB
1
LAN1
P1-DIMMA
1
P1-DIMMA
2
AL
WA
YS POPULA
TE DIMMx1 FIRST
IPMI_LAN
USB 4/5(3.0)
USB 0/1
P2-DIMMG
1
P2-DIMMH
1
P2-DIMMG
2
AL
WA
YS POPULA
TE DIMMx1 FIRST
P2-DIMMH
2
VGA
CPU2 SLOT
11
PCI-E 3.0 X8
CPU1 SLOT10 PCI-E 3.0 X8(IN X16)
PCH SLOT9 PCI-E 2.0 X4(IN X8
)
CPU2 SLOT8 PCI-E 3.0 X1
6
CPU2 SLOT6 PCI-E 3.0 X1
6
CPU1 SLOT4 PCI-E 3.0 X1
6
USB 7/8(3.0)
CPU1 SLOT2 PCI-E 3.0 X1
6
USB 2/3
JPWR
3
JPWR
1
JF
1
I-SGPIO
1
P1-DIMMD
1
CLOSE 1st
OPEN 1st
CLOSE 1st
OPEN 1st
LAN
CTRL
BMC
BIOS
PCH
LEDM1
JSTBY1
LED2
B
A
A. Internal Speaker
(Buzzer)
B. TPM/80 Port
Internal Speaker
The Internal Speaker (SP1) provides
audible indications for various beep
codes. See the table on the right for
pin definitions. Refer to the layout
below for the location of the internal
buzzer.
Internal Buzzer
Pin Definition
Pin# Definitions
Pin 1
Pos. (+)
Beep In
Pin 2
Neg. (-)
Alarm Speaker
TPM/Port 80 Header
A Trusted Platform Module/Port 80
header, located at JTPM1, provides
TPM support and Port 80 connection.
Use this header to enhance system
performance and data security. See
the table on the right for pin definitions.
TPM/Port 80 Header
Pin Definitions
Pin # Definition
Pin # Definition
1
LCLK
2
GND
3
LFRAME#
4
<(KEY)>
5
LRESET#
6
+5V (X)
7
LAD 3
8
LAD 2
9
+3.3V
10
LAD1
11
LAD0
12
GND
13
SMB_CLK4
14
SMB_DAT4
15
+3V_DUAL
16
SERIRQ
17
GND
18
CLKRUN# (X)
19
LPCPD#
20
LDRQ# (X)
