Chapter 2: Installation
2-29
Serial_Link-SGPIO
Pin Definitions
Pin# Definition
Pin Definition
1
NC
2
NC
3
Ground
4
DATA Out
5
Load
6
Ground
7
Clock
8
NC
T-SGPIO Headers (T-SGPIO1/2)
The T-SGPIO1 and T-SGPIO2 (Serial-
Link General Purpose Input/Output)
headers are located near the SATA
connectors on the motherboard. These
headers are used to communicate with
the enclosure management chip in the
system. See the table on the right for
pin definitions. Refer to the board layout
below for the locations of the headers.
10
9
2
1
BIOS LICENSE
1
3
JBT1
JSD1
1
3
JSTB
Y1
1
T-SGPIO1
1
2
7
8
T-SGPIO2
1
2
7
8
JTPM1
1
2
19
20
JPCIE
7
DIMM1
DIMM4
DIMM3
DIMM2
10
2
JPCI1
A1
B1
B2
JPCIE9
JUSBLAN2
JA
UDIO
1
J32
J15
2
1
7
J13
10
2
1
7
JD1
4
1
4
1
SP1
+
JWD1
JPL1
1
3
JPME2
1
3
JPME1
1
3
JPUSB1
13
JPUSB2
1
3
1
3
JCPUVRD_SMB
3
1
3
1
JPL2
3
1
R616
C
A
CA
TERR_LE
D
LED1
A
C
JPCIE6
B17
B18
A1
7
A1
8
JPCIE8
JPCIE5
J30
5
1
HDMI_
B1
+
C3102
JSPDIF_IN
JSPDIF_OUT
1
JL1
1
JI2C
2
1
JI2C
1
JUSB
4
11
10
19
1
B49
B48
A4
9
A4
8
Te
sted to
Co
mply
W
ith FC
C Standards
FOR HOME OR OFFICE US
E
MAC C
ODE
BAR C
ODE
MH3
MH4
MH9
MH5
MH1
MH2
MH6
MH7
MH8
1-2:RST
2-3:NMI
JWD1
JPL1
:
2-3:DISABLE 1-2:ENABLE
2-3:ME MANU
FA
CT
URING MODE
1-2:NORMA
L
JP
ME1:
2-3:ME RE
CO
VE
RY
JP
ME2:
1-2:NORMA
L
JPW3
JPL2
1-2:Enabl
e
2-3:Disable
USB3.0 1/
2
1-2:Enabl
e
JPUSB1:USB1
WA
KE UP
2-3:Disable
1-2:Enabl
e
JPUSB2:USB2
WA
KE UP
2-3:Disable
JP
AC
1
PCH SL
OT
2 PCI-E 2.0 X4 (INX8)
CPU1 SL
OT
7 PCI-E 2.0 X4
FANA
USB2/3
CMOS CLEA
R
SPEAKER:1-4
JD1:
BUZZER:3-4
JL1:
CHASSIS INTRUSION
PWR RST
JF1
ON
LED
X
OH/FF
NIC2
NIC1
HDD PWR
LED
LED
BUZZER
POWER LED
JLED
FAN3
FAN2
FAN1/CPU FAN
AL
WA
YS
POPUL
AT
E BL
UE SOCKE
T FIRS
T
AUDIO FP
JP
AC
1:A
UDIO
1-2:ENABLE
2-3:DISABLE
JPW2
JPW1
COM2
SL
OT
1 PCI 33MHZ
USB11/12
USB0/1
USB4/5
USB10/13
USB3.0 3/
4
COM1
VGA/
HDMI1/2
LAN2
LAN1
I-SATA0
I-SATA1
I-SATA2
I-SATA3
I-SATA4
I-SATA5
PCH SL
OT
3 PCI-E 2.0 X1
CPU1 SL
OT
4 PCI-E 3.0 X8 (INX16)
CPU1 SL
OT
6 PCI-E 3.0 X16
PCH SL
OT
5 PCI-E 2.0 X1
JI2C1/JI2C
2
OF
F:
Disable
ON:Enable
KB/MOUSE/USB8/
9
CPU
DIMMA1
DIMMB2
DIMMA2 DIMMB1
X9SAE
REV:1.01
DESIGNED IN USA
A
B
A. T-SGPIO1
B. T-SGPIO2
Summary of Contents for Supero X9SAE
Page 1: ...X9SAE X9SAE V USER S MANUAL Revision 1 0...
Page 26: ...1 14 X9SAE Motherboard Series User s Manual Notes...
Page 70: ...3 8 X9SAE Motherboard Series User s Manual Notes...
Page 96: ...A 2 X9SAE Motherboard Series User s Manual Notes...
Page 100: ...B 4 X9SAE Motherboard Series User s Manual Notes...