2-26
Supermicro C7Z370-CG-L Motherboard User’s Manual
TPM Header/Port 80
A Trusted Platform Module/Port 80 head-
er is located at JTPM1 to provide TPM
support and Port 80 connection. Use this
header to enhance system performance
and data security. See the table on the
right for pin definitions.
TPM/Port 80 Header
Pin Definitions
Pin # Definition
Pin # Definition
1
LCLK
2
GND
3
LFRAME#
4
<(KEY)>
5
LRESET#
6
+5V (X)
7
LAD 3
8
LAD 2
9
+3.3V
10
LAD1
11
LAD0
12
GND
13
SMB_CLK4
14
SMB_DAT4
15
+3V_DUAL
16
SERIRQ
17
GND
18
CLKRUN# (X)
19
LPCPD#
20
LDRQ# (X)
PCI-E M.2 Connector
The PCI-E M.2 connector is for PCI-E memory devices. These devices
must conform to the PCIE M.2 specifications (formerly known as NGFF).
COM1
RST
PWR
ON
OH/FF
X
NIC
1
HDD
LED
PWR
LED
JF1
TPM/PORT80
JTPM1:
JTPM1
JL1
TH1
USB 12/13(3.0)
JSTBY1
USB 4/5
USB 2/3
JBR1
LED BOOT
LED VGA
LED DIMM
CPU
LED
AUDIO FP
LED1
1-2:RST
2-3:NMI
JWD1:
JL1:
CHASSIS
INTRUSION
THERMAL SENSOR
TH1:
2-3:BIOS RECOVERY 1-2:NORMAL
J9701
J9702
JI2C1
JI2C2
WATCH DOG
5V STBY POWER
JSTBY1:
JBR1
OC1
OFF:DISABLE
JI2C1/JI2C2
ON :ENABLE
LED4
JWD1
PCH SLOT1 PCI-E 3.0 X4
2-3:DEBUG MODE
J9701/J9702
1-2:NORMAL
RESET
PCIE M.2 CONNECTOR 2
2260
1-2:NORMAL
2-3:ME MANUFACTURING MODE
JPME2:
2280
22110
CLEAR
BUTTON
SPEAKER:Pin1-4
JD1:
CMOS JSD1:SATA DOM PWR
POWER
PCH SLOT2 PCI-E 3.0 x1
PCH SLOT1 PCI-E 3.0 x4
JPME2
CPU SLOT3 PCI-E 3.0 x8 (IN x16)
JSD1
BUTTON
JD1
JBT1
JBT1:CMOS CLEAR
I-SATA4
I-SATA5
PCH SLOT4 PCI-E 3.0 x1
I-SATA2
I-SATA3
JSPDIF_OUT
PCH SLOT5 PCI-E 3.0 x1
I-SATA1
I-SATA0
CPU SLOT6 PCI-E 3.0 x16
PCIE M.2 CONNECTOR 1
SYS_FAN3
SYS_FAN2
HD AUDIO
2260
2280
22110
CPU
USB 6/7/8/9(3.0)
DVI
JPW1
JPUSB1:USB0/1 WAKE UP
HDMI/DP
2-3 DISABLE
1-2 ENABLE
DIMMB2
DIMMA2
DIMMB1
DIMMA1
CPU_FAN2
CPU_FAN1
JVR1
SYS_FAN1
JPW2
JPUSB1
KB/MOUSE USB 0/1
LED10
LED9
LED8
LED7
LED6
DESIGNED IN USA
REV:1.00
C7Z370-CG
-L
BIOS LICENSE
MAC CODE
BAR CODE
+
A
C
A
A
A
A
C
C
C
C
USB 10(3.1)
LAN
USB 11(3.1)
X
LED5
C
A
A
C
A. M.2 Connector 1
B. M.2 Connector 2
C. TPM Header
B
A
C
