Supermicro X7DBR-3, User Manual

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Chapter 1: Introduction
1-9
1-2 Chipset Overview
Built upon the functionality and the capability of the 5000P chipset, the X7DBR-3/
X7DBR-E motherboard provides the performance and feature set required for dual
processor-based servers with confi guration options optimized for communications,
presentation, storage, computation or database applications. The 5000P chipset
supports a single or dual Dempsey 64-bit dual core processor(s) with front side
bus speeds of up to 1.333 GHz. The chipset consists of the 5000P Memory Con-
troller Hub (MCH), the Enterprise South Bridge 2 (ESB2), and the I/O subsystem
(PXH-V).
The 5000P MCH chipset is designed for symmetric multiprocessing across two
independent front side bus interfaces. Each front side bus uses a 64-bit wide, 1333
MHz data bus that transfers data at 10.7 GB/sec. The MCH chipset connects up to
8 Fully Buffered DIMM modules, providing up to 32 GB of DDR2 FBD ECC memory.
The MCH chipset also provides three x8 PCI-Express interface to the ESB2. In
addition, the 5000P chipset offers a wide range of RAS features, including memory
interface ECC, x4/x8 Single Device Data Correction, CRC, parity protection, memory
mirroring and memory sparing.
Xeon Dual Core Processor Features
Designed to be used with conjunction of the 5000P chipset, the Xeon Dual Core
Processor provides a feature set as follows:
The Xeon Dual Core Processor
*L1 Cache Size: Instruction Cache (32KB/16KB), Data Cache (32KB/24KB)
*L2 Cache Size: 4MB (2MB per core)
*Data Bus Transfer Rate: 8.5 GB/s
*Package: FC-LGA6/FC-LGA4, 771 Lands