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X10DRFF/X10DRFF-C Motherboard User’s Manual
JPP1
S-SA
TA3
S-SA
TA2
J23
JPP2
JSD2
JSD1
S-SGPIO
S-SATA0
S-SATA1
I-SATA0
I-SATA1
I-SATA2
I-SATA3
I-SATA4
I-SATA5
JIPMB1
LED1
LED2
SP1
JBT1
LEDS1
JSTBY1
JUSB1
SW1
J3
COM1
JI2C1
JI2C2
JPB1
JPG1 JPME2
JPL2
JPL1
IPMI_LAN
JITP1
VGA
JP3
JP4
JP5
JUSB3
P1-DIMMC1 P1-DIMMD1
P2-DIMMG1 P2-DIMMH1
P1-DIMMA1
P1-DIMMB1
P2-DIMME1
P2-DIMMF1
BIOS
LICENSE
IPMI CODE
SAS CODE
MAC CODE
BAR CODE
L-SAS0-3
L-SAS4-7
JTPM1
JUIDB1
LAN2 LAN1
CPU1 SLOT1 PCI-E 3.0 X16
FAN2
FAN1
BATTERY
CPU2 SLOT2 PCI-E 3.0 X16
CPU2
CPU1
JUSB2
LEDM1
JPS1
I-SGPIO2
I-SGPIO1
X10DRFF(-C)
Rev. 1.02
1
1
1
1
Intel PCH
LSI 3008
SAS CTRL
AST2400
BMC
BIOS
JLAN1
JLAN2
IPMI_LAN1
JVGA1
LAN CTRL
LAN CTRL
JPCIE1
JPCIE2
JWD1
A. I-SGPIO 1 (for I-SATA 0-3)
B. I-SGPIO 2 (for I-SATA 4/5)
C. S-SGPIO (for S-SATA 0-3)
A
I-SGPIO 1/2 & S-SGPIO Headers
Three SGPIO (Serial-Link General Purpose
Input/Output) headers (I-SGPIO 1/2 & S-
SGPIO) are located on the motherboard.
I-SGPIO 1 supports Serial_Link interface for
onboard I- SATA 0-3, and I-SGPIO 2, I-SATA
4/5 connections. S-SGPIO supports S-SATA
0-3 from the Intel SCU. See the table on the
right for pin definitions.
T-SGPIO1/2, S-SGPIO
Pin Definitions
Pin# Definition
Pin# Definition
1
NC
2
NC
3
Ground
4
Data
5
Load
6
Ground
7
Clock
8
NC
B
C