Supermicro SUPERSERVER 6021H, User Manual, Page: 107 / 112

B-7
Appendix B: POST Checkpoint Codes
Checkpoint Code Description
98h The adaptor ROM had control and has now returned control to
BIOS POST. Performing any required processing after the option
ROM returned control.
99h Any initialization required after the option ROM test has com-
pleted.
Configuring the timer data area and printer base address next.
9Ah Set the timer and printer base addresses. Setting the RS-232
base address next.
9Bh Returned after setting the RS-232 base address. Performing any
required initialization before the Coprocessor test next.
9Ch Required initialization before the Coprocessor test is over.
Initializing the Coprocessor next.
9Dh Coprocessor initialized. Performing any required initialization after
the Coprocessor test next.
9Eh Initialization after the Coprocessor test is complete. Checking the
extended keyboard, keyboard ID, and Num Lock key next. Issuing
the keyboard ID command next.
A2h Displaying any soft errors next.
A3h The soft error display has completed. Setting the keyboard
typematic rate next.
A4h The keyboard typematic rate is set. Programming the memory
wait states next.
A5h Memory wait state programming is over. Clearing the screen and
enabling parity and the NMI next.
A7h NMI and parity enabled. Performing any initialization required
before passing control to the adaptor ROM at E000 next.
A8h Initialization before passing control to the adaptor ROM at E000h
completed. Passing control to the adaptor ROM at E000h next.
A9h Returned from adaptor ROM at E000h control. Performing any
initialization required after the E000 option ROM had control next.
Aah Initialization after E000 option ROM control has completed. Dis-
playing the system configuration next.
Abh Uncompressing the DMI data and executing DMI POST initialization
next.
B0h The system configuration is displayed.
B1h Copying any code to specific areas.
00h Code copying to specific areas is done. Passing control to INT
19h boot loader next.