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16
Chapter 1: Introduction
Figure 1-6. Motherboard Layout
1.4 Motherboard Layout
Below is a layout of the X12SPO-F motherboard with jumper, connector and LED locations
shown. See the table on the following page for descriptions. For detailed descriptions, pinout
information and jumper settings, refer to
or the
SAN MAC
BAR CODE
IPMI CODE
MAC CODE
BIOS
LICENSE
DESIGNED IN USA
X12SPO-NTF/-F
REV: 2.0
JIPMB1
JSTBY1
JP1
JCPLD1
JVRM1
JWD1
JP2
JD1
USB2/3
USB4/5
USB8/9 (3.0)
S-SA
TA0
I-SA
TA0-3
I-SA
TA4-7
JSD1
JSD2
S-SA
TA1
JL1
JF1
FANB
JLED1
S-SGPIO1
FANA
FAN4
FAN3
JRK1
NVMe8/9
JTPM1
M.2-H_1
M.2H_2
USB10 (3.0)
BT1
COM2
JNCSI1
JPL1
UID
VGA
LAN2
LAN1
USB6/7 (3.0)
IPMI_LAN
USB0/1
COM1
FAN5
JSEN1
NVMe4/5
NVMe2/3
NVMe0/1
JPWR1
JPWR2
JPI2C1
NVMe6/7
I-SA
TA0~3
I-SA
TA0~3
DIMMG1
DIMMF1
DIMMH1
DIMME1
DIMMA1
DIMMC1 DIMMD1
DIMMB1
CPU SLOT6 PCe 4.0 X16
FAN2
FAN1
JPWR3
BMC_HB_LED
POWER_LED
MH5
MH6
MH7
MH1
MH11
MH10
MH12
MH13
JNVI2C1
LED_CATERR
MH8
MH4
MH9
MH3
MH2
LED2
CPU
JPME2
IPMI_LAN
USB0/1
LAN1
USB6/7 (3.0)
LAN2
COM1
VGA
LED2
JPL1
JSEN1
JPWR3
JPI2C1
FAN2
DIMMF1
DIMMG1
DIMME1
DIMMH1
JVRM1
USB8/9 (3.0)
JF1
JPWR2
BT1
UID
SLOT6
DIMMC1
DIMMB1
DIMMD1
DIMMA1
JNVI2C1
COM2
USB2/3
BMC_HB_LED
JCPLD1
JTPM1
POWER_LED
CPU
JIPMB1
JSTBY1
JWD1
JD1
USB4/5
S-SATA0
JSD1
S_SATA1
JSD2
JL1
FANB
USB10
(3.0)
M.2-H_1
M.2-H_2
S-SGPIO1
FANA
FAN4
FAN3
JRK1
NVMe2/3
NVMe0/1
FAN1
JPWR1
FAN5
I-SATA4~7
I-SATA0~3
JLED1
LED_CATERR
JNCSI1
JPME2
Note:
the NVMe 4-9 headers are not included on the X12SPO-F.