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5-7
Chapter 5: BIOS
Core’s Enabled
Use this setting to specify the number of cores to enable. Use the number
pad “
+
” or “
-
” keys to specify a number up to 12. The number
0
means all
cores with 12 cores available.
Execute Disable Bit
Set to Enabled to enable the Execute Disable Bit which will allow the
processor to designate areas in the system memory where an application
code can execute and where it cannot, thus preventing a worm or a virus
from flooding illegal codes to overwhelm the processor and damage the
system during an attack. The default is
Enable
. (Refer to Intel and
Microsoft Web Sites for more information.)
PPIN Control
This setting is used to unlock and enable or disable PPIN control for your
system. Options include
Unlock/Enable
or Unlock/Disable.
Hardware Prefetcher
This setting lets you
Enable
or Disable the Hardware Prefetcher to
prefetch streams of data and instructions from the main memory to the L1
cache in order to improve CPU performance.
Adjacent Cache Prefetch
This setting lets you
Enable
or Disable the use of the Adjacent Prefetch to
prefetch streams of data and instructions from the main memory to the L1
cache in order to improve CPU performance.
DCU Streamer Prefetcher
This setting lets you
Enable
or Disable the DCU Streamer Prefetcher to
prefetch streams of data and instructions from the main memory to the L1
cache in order to improve CPU performance.
DCU IP Prefetcher
This setting lets you
Enable
or Disable the DCU IP Prefetcher to prefetch
streams of data and instructions from the main memory to the L1 cache in
order to improve CPU performance.
Direct Cache Access (DCA)
This setting enables direct cache access for your system. Options include
Auto
, Enable or Disable.
X2APIC
Use this setting to enable/disable extended APIC support for your system.
Options include
Disable
or Enable.
AES-NI
This setting
Enables
or Disables AES-NI support for your system.
Intel Virtualization
Technology
This setting
Enables
or Disables Vanderpool technology for your system
and takes effect only after a reboot.
Table 5-4. CPU Configuration Sub-menu (Continued)
Menu Option
Description
Summary of Contents for MicroBlade MBI-6119G-T7LX
Page 1: ...MBI 6219G T7LX MBI 6119G T7LX MicroBlade Module User s Manual Revison 1 0a...
Page 6: ...vii A 2 Standard Checkpoints A 2 A 3 OEM Reserved Checkpoint Ranges A 9...
Page 23: ...2 13 Chapter 2 Standardized Warning Statements...
Page 28: ...MBI 6219G T7LX MBI 6119G T7LX MicroBlade Module User s Manual 2 18 UL CSA Supermicro UL CSA...
Page 30: ...MBI 6219G T7LX MBI 6119G T7LX MicroBlade Module User s Manual 2 20...